18.4.5 DDR3PHY AC DLL Control Register

Name:	DDR3PHY_ACDLLCR
Offset:	0x14
Reset:	0x40000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	DLLDIS	DLLSRST
Access	R/W	R/W
Reset	0	1


Bit	23	22	21	20	19	18	17	16
						ATESTEN
Access						R/W
Reset						0


Bit	15	14	13	12	11	10	9	8
					MFWDLY[2:0]			MFBDLY[2]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
	MFBDLY[1:0]
Access	R/W	R/W
Reset	0	0

Bit 31 – DLLDIS DLL Disable

A disabled DLL is bypassed. Default ('0') is DLL enabled.

Bit 30 – DLLSRST DLL Soft Rest

Soft resets the AC DLL by driving the DLL soft reset pin.

Bit 18 – ATESTEN Analog Test Enable

Enables the analog test signal to be output on the DLL analog test output (test_out_a). The DLL analog test output is tri-stated when this bit is '0'.

Bits 11:9 – MFWDLY[2:0] Host Feed-Forward Delay Trim

Used to trim the delay in the host DLL feedforward path.

Value	Description
0	Minimum delay
1–6	Valid values, within range
7	Maximum delay

Bits 8:6 – MFBDLY[2:0] Host Feedback Delay Trim

Used to trim the delay in the host DLL feedback path.

Value	Description
0	Minimum delay
1–6	Valid values, within range
7	Maximum delay