18.4.67 DDR3PHY Data Byte DDR_D Timing Register

Name: DDR3PHY_DXxDQTR
Offset: 0x01D0 + x*0x40 [x=0..1]
Reset: 0x000000FF
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 DQDLY1[3:0]DQDLY0[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 11111111 

Bits 0:3, 4:7 – DQDLYx DDR_D Delay

Used to adjust the delay of the data relative to the nominal delay that is matched to the delay of the data strobes through the client DLL and clock tree. DQDLY0 controls the delay of data bit [0], DQDLY1 controls data bit [1].
ValueDescription
0 Nominal delay
1 Nominal delay + 1 step
2 Nominal delay + 2 steps
3 Nominal delay + 3 steps