18.4.10 DDR3PHY Data Byte Common Configuration Register


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
								AWDT
Access								R/W
Reset								0


Bit	15	14	13	12	11	10	9	8
	RVSEL	DQSNRST			DQSNRES[3:0]
Access	R/W	R/W			R/W	R/W	R/W	R/W
Reset	0	0			1	0	0	0


Bit	7	6	5	4	3	2	1	0
	DQSRES[3:0]				DXPDR	DXPDD	DXIOM	DXODT
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 16 – AWDT Active Window Data Train

If set, indicates that data training (DDR_DQS gate training and read valid training) must be performed with active DDR_DQS gate window. The default is to perform training with passive windowing.

Bit 15 – RVSEL ITMD Read Valid Select

Selects the scheme used for ITMD read valid.

Value	Description
0	ITMD read valid signal is generated by delayed DFI read enable signal.
1	ITMD read valid is generated by the ITMD itseld using asynchronous crossing.

Bit 14 – DQSNRST DDR_DQSN Reset

If set, indicates that the ITMS of DDR_DQSN must always be put in reset such that its output enable is always '1' and its data output is always '0'. This is done by driving the oe_set_b and do_rst_b pins of this ITMS to '0' in order to force the unused DDR_DQSN PAD to a known state of '0' in applications that don't use DDR_DQSN such as in LPDDR mode.

Bits 11:8 – DQSNRES[3:0] DDR_DQSN Resistor

Selects the on-die pull-up/pull-down resistor for DDR_DQSN pins. Same encoding as DQSRES.

Note: DDR_DQSN resistor must be connected for LPDDR2.

Bits 7:4 – DQSRES[3:0] DDR_DQS Resistor

Note: DDR_DQS resistor must be connected for LPDDR2.

Selects the on-die pull-down/pull-up resistor for DDR_DQS pins.

DQSRES[3] selects pull-down (when set to '0') or pull-up (when set to '1').

DQSRES[2:0] selects the resistor value as follows:

Value	Description
0	Open: On-die resistor disconnected
1	688 ohms
2	611 ohms
3	550 ohms
4	500 ohms (recommended value)
5	458 ohms
6	393 ohms
7	344 ohms

Bit 3 – DXPDR Data Power Down Receiver

When set, powers down the input receiver on I/O for DDR_D, DDR_DQM, and DDR_DQS/DDR_DQSN pins. This bit is global for all data bytes.

Bit 2 – DXPDD Data Power Down Driver

When set, powers down the output driver on I/O for DDR_D, DDR_DQM, and DDR_DQS/DDR_DQSN pins. This bit is global for all data bytes.

Bit 1 – DXIOM Data I/O Mode

Must be written to '0'.

Bit 0 – DXODT Data On-Die Termination

When set, enables the on-die termination on the I/O for DDR_D, DDR_DQM, and DDR_DQS/DDR_DQSN pins. This bit is global for all data bytes.

Name:	DDR3PHY_DXCCR
Offset:	0x28
Reset:	0x00000800
Property:	Read/Write