18.4.59 DDR3PHY ZQ Impedance Control Register 0


Bit	31	30	29	28	27	26	25	24
	ZQPD	ZCAL	ZCALBYP	ZDEN	ZDATA[27:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	ZDATA[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ZDATA[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	1


Bit	7	6	5	4	3	2	1	0
	ZDATA[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	1	0	0	1	0	1	0

Bit 31 – ZQPD ZQ Power Down

If set, powers down the PZQ cell.

Bit 30 – ZCAL Impedance Calibration Trigger

A write of '1' to this bit triggers impedance calibration to be performed by the impedance control logic. The impedance calibration trigger bit is self-clearing and returns back to '0' when the calibration is complete.

Note: If ZDEN is set, then the ZCAL bit must be set to 0.

Bit 29 – ZCALBYP Impedance Calibration Bypass

If set, disables impedance calibration of this DDR_ZQ control block when impedance calibration is triggered globally using ZCAL. Impedance calibration of this DDR_ZQ block may be triggered manually using ZCAL.

Bit 28 – ZDEN Impedance Override Enable

When this bit is set, it allows users to directly drive the impedance control using the data programmed in the ZQDATA field. Otherwise, the control is generated automatically by the impedance control logic.

Note: If ZDEN is set, then the ZCAL bit must be set to 0.

Bits 27:0 – ZDATA[27:0] Impedance Override Data

Data used to directly drive the impedance control. Field mapping is as follows:


Value	Description
[27:20]	Reserved, returns zeros on reads
[19:15]	Pull-up on-die termination impedance select
[14:10]	Pull-down on-die termination impedance select
[9:5]	Pull-up output impedance select
[4:0]	Pull-down output impedance select

Name:	DDR3PHY_ZQ0CR0
Offset:	0x180
Reset:	0x0000014A
Property:	Read/Write