18.4.64 DDR3PHY Data Byte General Status Register 0

Name:	DDR3PHY_DXxGSR0
Offset:	0x01C4 + x*0x40 [x=0..1]
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	DTPASS[2:0]							DTIERR
Access	R/W	R/W	R/W					R/W
Reset	0	0	0					0


Bit	7	6	5	4	3	2	1	0
				DTERR				DTDONE
Access				R/W				R/W
Reset				0				0

Bits 15:13 – DTPASS[2:0] DDR_DQS GateTraining Pass Count

The number of passing configurations during DDR_DQS gate training.

Bit 8 – DTIERR DDR_DQS Gate Training Intermittent Error

If set, indicates that there was an intermittent error during DDR_DQS gate training of the byte, such as a pass was followed by a fail then followed by another pass.

Bit 4 – DTERR DDR_DQS Gate Training Error

If set, indicates that a valid DDR_DQS gating window could not be found during DDR_DQS gate training of the byte.

Bit 0 – DTDONE Data Training Done

If set, indicates that the byte has finished doing data training.