18.4.1 DDR3PHY PHY Initialization Register
Name: | DDR3PHY_PIR |
Offset: | 0x04 |
Reset: | 0x00000000 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
INITBYP | ZCALBYP | LOCKBYP | CLRSR | ||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
CTLDINIT | DLLBYP | ICPC | |||||||
Access | R/W | R/W | R/W | ||||||
Reset | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
RVTRN | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
QSTRN | DRAMINIT | DRAMRST | ITMSRST | ZCAL | DLLLOCK | DLLSRST | INIT | ||
Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – INITBYP Initialization Bypass
Bit 30 – ZCALBYP Impedance Calibration Bypass
Bit 29 – LOCKBYP DLL Lock Bypass
Bit 28 – CLRSR Clear Status Registers
Writing 1 to this bit does the following:
- Auto-clears itself (CLRSR). This means that any reads to this bit will return 0.
- Clears bits DTDONE, DTERR, DTIERR in DDR3PHY_DXnGSR0.
- Clears DDR3PHY_PGSR.DFTERR and DDR3PHY_DXnGSR1.DFTERR.
This bit is primarily for debug purposes and is typically not needed during normal functional operation. It can be used when DDR3PHY_PGSR.IDONE=1, to manually clear the DDR3PHY_PGSR status bits, however, the DDR3PHY_PGSR status bits (except for DDR3PHY_PGSR.DFTERR) are automatically cleared by starting a new init process.
The bit can also be used to manually clear the DDR3PHY_DXnGSR status bits, however, starting a new data training process automatically clears DDR3PHY_DXnGSR status bits.
Bit 18 – CTLDINIT Controller DRAM Initialization
Bit 17 – DLLBYP DLL Bypass
Bit 16 – ICPC Initialization Complete Pin Configuration
Value | Description |
---|---|
0 | Asserted after DDR3PHY initialization (DLL locking and impedance calibration) is complete. |
1 | Asserted after DDR3PHY initialization is complete and the triggered the DDR3PHY initialization (DRAM initialization, data training, or initialization trigger with no selected initialization) is complete. |
Bit 8 – RVTRN RV Training
This bit and Read DDR_DQS Gate Training (DDR3PHY_PIR.QSTRN) must be run together. RVTRN is set whenever DDR3PHY_PIR.QSTRN is set.
If RVTRN=1 and DDR3PHY_PIR.QSTRN=0, when INIT=1 (triggering the init process), the read DDR_DQS gate training algorithm runs (as if DDR3PHY_PIR.QSTRN were actually set to 1).
If it is necessary to run only RV training stand-alone, with no read DDR_DQS gate training, running the read DDR_DQS gate training can be prevented by setting DDR3PHY_PGCR.LBGDQS=1 (see DDR3PHY_PGCR).
Bit 7 – QSTRN Read DDR_DQS Training
Bit 6 – DRAMINIT DRAM Initialization
Bit 5 – DRAMRST DRAM Reset (DDR3 Only)
Bit 4 – ITMSRST Interface Timing Module Soft Reset
Bit 3 – ZCAL Impedance Calibrate
Bit 2 – DLLLOCK DLL Lock
Bit 1 – DLLSRST DLL Soft Reset
Requires that DDRPLL is toggling for the DLL soft reset signal to be output from the DLL. If DDRPLL is not guaranteed to be toggling, it is recommended to use the manual DLL soft reset DDR3PHY_ACDLLCR.DLLSRST, not DDR3PHY_PIR.DLLSRST.
Ensure that the minimum requirements for DLL bypass and DLL reset are observed while asserting this bit.