18.4.1 DDR3PHY PHY Initialization Register

Name: DDR3PHY_PIR
Offset: 0x04
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
 INITBYPZCALBYPLOCKBYPCLRSR     
Access R/WR/WR/WR/W 
Reset 0000 
Bit 2322212019181716 
      CTLDINITDLLBYPICPC 
Access R/WR/WR/W 
Reset 000 
Bit 15141312111098 
        RVTRN 
Access R/W 
Reset 0 
Bit 76543210 
 QSTRNDRAMINITDRAMRSTITMSRSTZCALDLLLOCKDLLSRSTINIT 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 31 – INITBYP Initialization Bypass

If set, bypasses or stops all initialization routines currently running, including DDR3PHY initialization, DRAM initialization, and DDR3PHY training. Initialization may be triggered manually using DDR3PHY_PIR.INIT and the other relevant bits of this register. This bit is self-clearing.

Bit 30 – ZCALBYP Impedance Calibration Bypass

If set, bypasses or stops impedance calibration of all DDR_ZQ control blocks that automatically trigger after reset. Impedance calibration may be triggered manually using DDR3PHY_PIR.INIT and DDR3PHY_PIR.ZCAL bits. This bit is self-clearing.

Bit 29 – LOCKBYP DLL Lock Bypass

If set, bypasses or stops the waiting of DLLs to lock. The DLL lock wait is automatically triggered after reset. It may be triggered manually using DDR3PHY_PIR.INIT and DDR3PHY_PIR.DLLLOCK bits. This bit is self-clearing.

Bit 28 – CLRSR Clear Status Registers

Writing 1 to this bit does the following:

- Auto-clears itself (CLRSR). This means that any reads to this bit will return 0.

- Clears bits DTDONE, DTERR, DTIERR in DDR3PHY_DXnGSR0.

- Clears DDR3PHY_PGSR.DFTERR and DDR3PHY_DXnGSR1.DFTERR.

This bit is primarily for debug purposes and is typically not needed during normal functional operation. It can be used when DDR3PHY_PGSR.IDONE=1, to manually clear the DDR3PHY_PGSR status bits, however, the DDR3PHY_PGSR status bits (except for DDR3PHY_PGSR.DFTERR) are automatically cleared by starting a new init process.

The bit can also be used to manually clear the DDR3PHY_DXnGSR status bits, however, starting a new data training process automatically clears DDR3PHY_DXnGSR status bits.

Bit 18 – CTLDINIT Controller DRAM Initialization

If set, indicates that DRAM initialization is performed by the controller. If not set, indicates that DRAM initialization is performed using the built-in initialization sequence or using software through the configuration port.

Bit 17 – DLLBYP DLL Bypass

If set, all DDR3PHY DLLs are put in Bypass mode. A bypassed DLL is also powered down (disabled).
Note: Ensure that the minimum requirements for DLL bypass and DLL reset are observed while asserting this bit.

Bit 16 – ICPC Initialization Complete Pin Configuration

Specifies how the initialization complete output pin must be used to indicate the status of initialization.
ValueDescription
0 Asserted after DDR3PHY initialization (DLL locking and impedance calibration) is complete.
1 Asserted after DDR3PHY initialization is complete and the triggered the DDR3PHY initialization (DRAM initialization, data training, or initialization trigger with no selected initialization) is complete.

Bit 8 – RVTRN RV Training

This bit and Read DDR_DQS Gate Training (DDR3PHY_PIR.QSTRN) must be run together. RVTRN is set whenever DDR3PHY_PIR.QSTRN is set.

If RVTRN=1 and DDR3PHY_PIR.QSTRN=0, when INIT=1 (triggering the init process), the read DDR_DQS gate training algorithm runs (as if DDR3PHY_PIR.QSTRN were actually set to 1).

If it is necessary to run only RV training stand-alone, with no read DDR_DQS gate training, running the read DDR_DQS gate training can be prevented by setting DDR3PHY_PGCR.LBGDQS=1 (see DDR3PHY_PGCR).

Note: RV Training cannot use the DDR3 Multi-Purpose register (MPR) and must use the user data programmed in DDR3PHY_DTDR0/1. Refer to the memory vendor data sheet for details.

Bit 7 – QSTRN Read DDR_DQS Training

Executes a DDR3PHY training routine to determine the optimum position of the read data DDR_DQS strobe for maximum system timing margins.

Bit 6 – DRAMINIT DRAM Initialization

Executes the DRAM initialization sequence.

Bit 5 – DRAMRST DRAM Reset (DDR3 Only)

Issues a reset to the DRAM (by driving the DRAM reset pin low) and waits 200 µs. This can be triggered in isolation or with the full DRAM initialization (DDR3PHY_PIR.DRAMINIT). For the latter case, the reset is issued and 200 µs is waited before starting the full initialization sequence.

Bit 4 – ITMSRST Interface Timing Module Soft Reset

Soft resets the interface timing modules for the data and data strobes, i.e., it asserts the ITM soft reset (srstb) signal.

Bit 3 – ZCAL Impedance Calibrate

Performs DDR3PHY impedance calibration.

Bit 2 – DLLLOCK DLL Lock

Waits for the DDR3PHY DLLs to lock.

Bit 1 – DLLSRST DLL Soft Reset

Soft resets all DDR3PHY DLLs by driving the DLL soft reset pin.

Requires that DDRPLL is toggling for the DLL soft reset signal to be output from the DLL. If DDRPLL is not guaranteed to be toggling, it is recommended to use the manual DLL soft reset DDR3PHY_ACDLLCR.DLLSRST, not DDR3PHY_PIR.DLLSRST.

Ensure that the minimum requirements for DLL bypass and DLL reset are observed while asserting this bit.

Bit 0 – INIT Initialization Trigger

A write of '1' to this bit triggers the DDR system initialization, including DDR3PHY initialization, DRAM initialization, and DDR3PHY training. The exact initialization steps to be executed are specified in bits 1 to 6 of this register. A bit setting of '1' means the step will be executed as part of the initialization sequence, while a setting of ‘0’ means the step will be bypassed. The initialization trigger bit is self-clearing.