18.4.23 DDR3PHY Mode Register 2 (MR2/EMR2) (DDR2 Mode)

Name:	DDR3PHY_MR2_DDR2
Offset:	0x48
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	RSVD[4:0]
Access	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	SRF				DCC	PASR[2:0]
Access	R/W				R/W	R/W	R/W	R/W
Reset	0				0	0	0	0

Bits 15:11 – RSVD[4:0] Reserved

These are JEDEC reserved bits and are recommended by JEDEC to be programmed to ‘0’

Bit 7 – SRF Self-Refresh Rate

If set, enables high-temperature self-refresh rate.

Bit 3 – DCC Duty Cycle Corrector

If set, enables duty cycle correction within SDRAM.

Bits 2:0 – PASR[2:0] Partial Array Self-Refresh

Specifies that data located in areas of the array beyond the specified location will be lost if self-refresh is entered.

Value	Description
	Valid settings for 4 banks:
0	Full array
1	Half array (DDR_BA[1:0] = 00 & 01)
2	Quarter array (DDR_BA[1:0] = 00)
3	Not defined
4	3/4 array (DDR_BA[1:0] = 01, 10, & 11)
5	Half array (DDR_BA[1:0] = 10 & 11)
6	Quarter array (DDR_BA[1:0] = 11)
7	Not defined
	Valid settings for 8 banks:
0	Full array
1	Half array (DDR_BA[2:0] = 000, 001, 010 & 011)
2	Quarter array (DDR_BA[2:0] = 000, 001)
3	1/8 array (DDR_BA[2:0] = 000)
4	3/4 array (DDR_BA[2:0] = 010, 011, 100, 101, 110 & 111)
5	Half array (DDR_BA[2:0] = 100, 101, 110 & 111)
6	Quarter array (DDR_BA[2:0] = 110 & 111)
7	1/8 array (DDR_BA[2:0] 111)

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