Jump to main content
18.4.44 DDR3PHY BIST Mask 0
Register Name: DDR3PHY_BISTMSKR0 Offset: 0x104 Reset: 0x00000000 Property: Read/Write
Bit 31 30 29 28 27 26 25 24 ODTMSK CSMSK Access R/W R/W Reset 0 0
Bit 23 22 21 20 19 18 17 16 CKEMSK WEMSK BAMSK[2:0] Access R/W R/W R/W R/W R/W Reset 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 AMSK[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 AMSK[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 28 – ODTMSK
Bit 24 – CSMSK DDR_CSN Mask Bit
Bit 20 – CKEMSK DDR_CKE Mask Bit
Bit 19 – WEMSK DDR_WEN Mask Bit
Bits 18:16 – BAMSK[2:0] DDR_BA Mask
Bit Mask bit for each
DDR_BA[2:0].
Bits 15:0 – AMSK[15:0] DDR_A Mask Bit
Mask bit for each DDR_A[15:0].
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
