18.4.41 DDR3PHY DCU Status Register 1

Name:	DDR3PHY_DCUSR1
Offset:	0xDC
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	LPCNT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	FLCND[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	RDCNT[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	RDCNT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:24 – LPCNT[7:0] Loop Count

Indicates the value of the loop count. This is useful when the program has stooped because of failures to assess how many reads were executed before first fail.

Bits 23:16 – FLCND[7:0] Fail Count

Number of read words that have failed.

Bits 15:0 – RDCNT[15:0] Read Count

Number of read words returned from the SDRAM.