18.4.15 DDR3PHY DRAM Timing Parameter Register 2
| Name: | DDR3PHY_DTPR2 |
| Offset: | 0x3C |
| Reset: | 0x1001A0C8 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | TDLLK[9:5] | |
| Access | | | | R/W | R/W | R/W | R/W | R/W | |
| Reset | | | | 1 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | TDLLK[4:0] | TCKE[3:1] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | TCKE[0] | TXP[4:0] | TXS[9:8] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | TXS[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | |
Bits 28:19 – TDLLK[9:0] DLL Locking
Time
Valid values are 2 to
1023.
Bits 18:15 – TCKE[3:0] DDR_CKE Minimum Pulse
Width
Also specifies the minimum time
that the SDRAM must remain in Power-down or Self-refresh mode. For DDR3, this
parameter must be set to the value of tCKESR which is usually greater
than the value of tCKE. Valid values are 2 to 15.
Bits 14:10 – TXP[4:0] Power-Down Exit
Delay
The minimum time between a
power-down exit command and any other command. This parameter must be set to the
maximum of the various minimum power-down exit delay parameters specified in the
SDRAM memory device data sheet, i.e. max(tXP, tXARD,
tXARDS) for DDR2 and max(tXP, tXPDLL) for DDR3.
Valid values are 2 to 31.
Bits 9:0 – TXS[9:0] Self-Refresh Exit
Delay
The minimum time between a
self-refresh exit command and any other command. This parameter must be set to the
maximum of the various minimum self-refresh exit delay parameters specified in the
SDRAM memory device data sheet, i.e. max(tXSNR, tXSRD) for
DDR2 and max(tXS, tXSDLL) for DDR3. Valid values are 2 to
1023.
