18.4.42 DDR3PHY BIST Run Register


Bit	31	30	29	28	27	26	25	24
							BCKSEL[2:1]
Access							R/W	R/W
Reset							0	0


Bit	23	22	21	20	19	18	17	16
	BCKSEL[0]				BDXSEL	BDPAT[1:0]		BDMEN
Access	R/W				R/W	R/W	R/W	R/W
Reset	0				0	0	0	0


Bit	15	14	13	12	11	10	9	8
	BACEN	BDXEN	BSONF	NFAIL[7:3]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	NFAIL[2:0]			BINF	BMODE	BINST[2:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 25:23 – BCKSEL[2:0] BIST DDR_CLK Select

Selects the DDR_CLK to be used for capturing loopback data on the address/command lane.

Value	Description
0	DDR_CLK
1	Reserved
2	Reserved
3	Reserved
4	DDR_CLKN
5	Reserved
6	Reserved
7	Reserved

Bit 19 – BDXSEL BIST Data Byte Lane Select

Selects the byte lane for comparison of loopback/read data.

Bits 18:17 – BDPAT[1:0] BIST Data Pattern

Selects the data pattern used during BIST.

Value	Description
0	Walking 0
1	Walking 1
2	LFSR-based pseudo-random
3	User programmable

Bit 16 – BDMEN BIST Data Mask Enable

If set, enables the data mask BIST to be included in the BIST run, i.e. data pattern generated and loopback data compared. This is valid only for Loopback mode.

Bit 15 – BACEN BIST AC Enable

Enables the running of BIST on the address/command lane PHY. This bit is exclusive with BDXEN, i.e. both cannot be set to '1' at the same time.

Bit 14 – BDXEN BIST Data Enable

Enables the running of BIST on the data byte lane PHYs. This bit is exclusive with BACEN, i.e. both cannot be set to '1' at the same time.

Bit 13 – BSONF BIST Stop On Nth Fail

If set, specifies that the BIST stops when an nth data word or address/command comparison error has been encountered.

Bits 12:5 – NFAIL[7:0] Number of Failures

Specifies the number of failures after which the execution of commands and the capture of read data stop if BSONF is set. Execution of commands and the capture of read data will stop after (NFAIL+1) failures if BSONF is set.

Bit 4 – BINF BIST Infinite Run

If set, specifies that the BIST runs indefinitely until when it is either stopped or a failure has been encountered. Otherwise, BIST is run until number of BIST words specified in DDR3PHY_BISTWCR has been generated.

Bit 3 – BMODE BIST Mode

Selects the mode in which BIST is run.

Value	Name	Description
0	Loopback mode	Address, commands and data loop back at the PHY I/Os.
1	DRAM mode	Address, commands and data go to DRAM for normal memory accesses.

Bits 2:0 – BINST[2:0] BIST Instruction

Selects the BIST instruction to be executed.

Value	Name	Description
0	NOP	No operation
1	Run	Triggers the running of the BIST
2	Stop	Stops the running of the BIST
3	Reset	Resets all BIST run-time registers, such as error counters
4–7	–	Reserved

Name:	DDR3PHY_BISTRR
Offset:	0x100
Reset:	0x00000000
Property:	Read/Write