18.4.13 DDR3PHY DRAM Timing Parameters Register 0


Bit	31	30	29	28	27	26	25	24
	TCCD	TRC[5:0]						TRRD[3]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	1	1	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	TRRD[2:0]			TRAS[4:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	0	0	1	0	0	1	0


Bit	15	14	13	12	11	10	9	8
	TRCD[3:0]				TRP[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	1	1	0	0	1	1	0


Bit	7	6	5	4	3	2	1	0
	TWTR[2:0]			TRTP[2:0]			TMRD[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	1	1	0	1	1	1	0

Bit 31 – TCCD Read to Read and Write to Write Command Delay

Value	Description
0	BL/2 for DDR2 and 4 for DDR3
1	BL/2 + 1 for DDR2 and 5 for DDR3

Bits 30:25 – TRC[5:0] Activate to Activate Command Delay (same bank)

Activate to activate command delay (same bank). Valid values are 2 to 42.

Bits 24:21 – TRRD[3:0] Activate to Activate Command Delay (different banks)

Activate to activate command delay (different banks). Valid values are 1 to 8.

Bits 20:16 – TRAS[4:0] Activate to Precharge Command Delay

Valid values are 2 to 31.

Bits 15:12 – TRCD[3:0] Activate to Read or Write Delay

Minimum time from when an activate command is issued to when a read or write to the activated row can be issued. Valid values are 2 to 11.

Bits 11:8 – TRP[3:0] Precharge Command Period

The minimum time between a precharge command and any other command. Note that the controller automatically derives t_RPA for 8-bank DDR2 devices by adding 1 to t_RP. Valid values are 2 to 11.

Bits 7:5 – TWTR[2:0] Internal Write to Read Command Delay

Internal write to read command delay. Valid values are 1 to 6.

Bits 4:2 – TRTP[2:0] Internal Read to Precharge Command Delay

Internal read to precharge command delay. Valid values are 2 to 6. Note that even though RTP does not apply to JEDEC DDR devices, this parameter must still be set to a minimum value of 2 for DDR because the controller always uses the DDR2 equation, AL + BL/2 + max(RTP, 2) – 2, to compute the read to precharge timing (which is BL/2 for JEDEC DDR).

Bits 1:0 – TMRD[1:0] Load Mode Cycle Time

The minimum time between a Load Mode register command and any other command. For DDR3, this is the minimum time between two Load Mode register commands. Valid values for DDR2 are 2 to 3. For DDR3, the value used for t_MRD is 4 plus the value programmed in these bits, i.e. t_MRD value for DDR3 ranges from 4 to 7. For LPDDR3, the value used for t_MRD is 8 plus the value programmed in these bits.

Name:	DDR3PHY_DTPR0
Offset:	0x34
Reset:	0x3092666E
Property:	Read/Write