18.4.56 DDR3PHY BIST Word Count Status Register

Name:	DDR3PHY_BISTWCSR
Offset:	0x138
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	DXWCNT[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DXWCNT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ACWCNT[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ACWCNT[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:16 – DXWCNT[15:0] Byte Word Count

Indicates the number of words received from the byte lane.

Bits 15:0 – ACWCNT[15:0] Address/Command Word Count

Indicates the number of words received from the address/command lane.

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