18.4.33 DDR3PHY Data Training Data Register 1

Name:	DDR3PHY_DTDR1
Offset:	0x5C
Reset:	0x7788BB44
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	DTBYTE7[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	1	1	1	0	1	1	1


Bit	23	22	21	20	19	18	17	16
	DTBYTE6[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	0	0	0	1	0	0	0


Bit	15	14	13	12	11	10	9	8
	DTBYTE5[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	0	1	1	1	0	1	1


Bit	7	6	5	4	3	2	1	0
	DTBYTE4[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	1	0	0	0	1	0	0

Bits 31:24 – DTBYTE7[7:0] Data Training Data

The second 4 bytes of data used during data training. This same data byte is used for each byte lane. Default sequence is a walking 1 while toggling data every data cycle.

Bits 23:16 – DTBYTE6[7:0] Data Training Data

The second 4 bytes of data used during data training. This same data byte is used for each byte lane. Default sequence is a walking 1 while toggling data every data cycle.

Bits 15:8 – DTBYTE5[7:0] Data Training Data

The second 4 bytes of data used during data training. This same data byte is used for each byte lane. Default sequence is a walking 1 while toggling data every data cycle.

Bits 7:0 – DTBYTE4[7:0] Data Training Data

The second 4 bytes of data used during data training. This same data byte is used for each byte lane. Default sequence is a walking 1 while toggling data every data cycle.