18.4.50 DDR3PHY BIST User Data Pattern Register

Name:	DDR3PHY_BISTUDPR
Offset:	0x120
Reset:	0xFFFF0000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	BUDP1[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	1	1	1	1


Bit	23	22	21	20	19	18	17	16
	BUDP1[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	1	1	1	1


Bit	15	14	13	12	11	10	9	8
	BUDP0[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	BUDP0[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:16 – BUDP1[15:0] BIST User Data Pattern 1

Data to be applied on odd DDR_D pins during BIST.

Bits 15:0 – BUDP0[15:0] BIST User Data Pattern 0

Data to be applied on even DDR_D pins during BIST.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.