18.4.19 DDR3PHY Mode Register 1 (MR1) (DDR2 Mode)


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
				QOFF	RDQS	DQS	OCD[2:1]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	OCD[0]	RTT1	AL[2:0]			RTT0	DIC	DE
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 12 – QOFF Output Enable/Disable

When ‘0’, all outputs function normal, when ‘1’ all SDRAM outputs are disabled removing output buffer current. This feature is intended to be used for IDD characterization of read current and must not be used in normal operation.

Bit 11 – RDQS RDQS Enable/Disable

Must be written to '0'.

Bit 10 – DQS DDR_DQSN Enable/Disable

Must be written to '0'.

Bits 9:7 – OCD[2:0] Off-Chip Driver (OCD) Impedance Calibration

Used to calibrate and match pull-up to pull-down impedance to 18 Ω nominal (refer to the SDRAM memory device data sheet for details). Note that OCD is not supported by all vendors. Refer to the SDRAM memory device data sheet for details on the recommended OCD settings. Valid values are as follows. All other settings are reserved and must not be used.

Value	Description
0	OCD calibration mode exit
1	Drive (1) pull-up
2	Drive (0) pull-down
4	OCD enter adjust mode
7	OCD calibration default

Bit 6 – RTT1 On-Die Termination

Selects the resistance for SDRAM on-die termination.

RTT1–RTT0: Valid values are as follows.

Value	Description
0	ODT disabled
1	75 Ω
2	150 Ω
3	50 Ω (some vendors)

Bits 5:3 – AL[2:0] Posted CAS Additive Latency

Setting additive latency that allows read and write commands to be issued to the SDRAM earlier than normal (refer to the SDRAM memory device data sheet for details). Valid values are as follows. All other settings are reserved and must not be used. The maximum allowed value of AL is t_RCD-1.

Value	Description
0	0
1	1
2	2
3	3
4	4
5	5

Bit 2 – RTT0 On-Die Termination

Selects the resistance for SDRAM on-die termination. See RTT1.

Bit 1 – DIC Output Driver Impedance Control

Controls the output drive strength.

Value	Description
0	Full strength
1	Reduced strength

Bit 0 – DE DLL Enable/Disable

DLL must be enabled for normal operation.

Value	Description
0	Enable the DLL
1	Disable the DLL

Name:	DDR3PHY_MR1_DDR2
Offset:	0x44
Reset:	0x00000000
Property:	Read/Write