18.4.29 DDR3PHY Mode Register 3 (MR3) (LPDDR3 Mode)

Name:	DDR3PHY_MR3_LPDDR3
Offset:	0x4C
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	RSVD[3:0]				PDCTL[1:0]		DQODT[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:4 – RSVD[3:0] Reserved

These are JEDEC reserved bits and are recommended by JEDEC to be programmed to ‘0’.

Bits 3:2 – PDCTL[1:0] Power-Down Control

Value	Description
0	ODT disabled by DRAM during power.
1	ODT enabled by DRAM during power-down.

Bits 1:0 – DQODT[1:0] On-Die Termination

Value	Description
0	Disable (default)
1	R_ZQ/4 (optional for LPDDR3-1066 devices)
2	R_ZQ/2
3	R_ZQ/1

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