18.4.17 DDR3PHY Mode Register 0 (MR0) (DDR2 Mode)


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
				PD	WR[2:0]			DR
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	1	0	1	0


Bit	7	6	5	4	3	2	1	0
	TM	CL[2:0]			BT	BL[2:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	1	0	1	0	0	1	0

Bit 12 – PD Power-Down Control

Controls the exit time for Power-Down modes. Refer to the SDRAM memory device data sheet for details on Power-Down modes.

Value	Description
0	Fast exit
1	Slow exit

Bits 11:9 – WR[2:0] Write Recovery

This is the value of the write recovery in clock cycles. It is calculated by dividing the datasheet write recovery time, t_WR (ns) by the data sheet DDR clock period (ns) and rounding up a non-integer value to the next integer.

Note: t_WR (ns) is the time from the first SDRAM positive clock edge after the last data-in pair of a write command, to when a precharge of the same bank can be issued.

Valid values are as follows. All other settings are reserved and must not be used.

Value	Description
1	2
2	3
3	4
4	5
5	6

Bit 8 – DR DLL Reset

Writing a ‘1’ to this bit resets the SDRAM DLL. This bit is self-clearing, i.e. it returns back to ‘0’ after the DLL reset has been issued.

Bit 7 – TM Operating Mode

Value	Description
0	Normal operating mode
1	Test mode. Test mode is reserved for the manufacturer and must not be used.

Bits 6:4 – CL[2:0] CAS Latency

The delay, in clock cycles, between when the SDRAM registers a read command to when data is available. Valid values are as follows. All other settings are reserved and must not be used.

Value	Description
2	2
3	3
4	4
5	5
6	6

Bit 3 – BT Burst Type

Indicates whether a burst is sequential or interleaved.

Value	Description
0	Sequential burst
1	Interleaved burst

Bits 2:0 – BL[2:0] Burst Length

Determines the maximum number of column locations that can be accessed during a given read or write command. Valid values are as follows. All other settings are reserved and must not be used.

Value	Description
2	4
3	8

Name:	DDR3PHY_MR0_DDR2
Offset:	0x40
Reset:	0x00000A52
Property:	Read/Write