18.4.22 DDR3PHY Mode Register 2 (MR2/EMR2) (DDR3 Mode)


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	RSVD[4:0]					RTTWR[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	SRT	ASR	CWL[2:0]			PASR[2:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:11 – RSVD[4:0] Reserved

These are JEDEC reserved bits and are recommended by JEDEC to be programmed to ‘0’.

Bits 10:9 – RTTWR[1:0] Dynamic ODT

Selects RTT for dynamic ODT.

Value	Description
0	Dynamic ODT off
1	R_ZQ/4
2	R_ZQ/2
3	Reserved

Bit 7 – SRT Self-Refresh Temperature Range

Selects either normal or extended operating temperature range during self-refresh.

Value	Description
0	Normal self-refresh temperature range
1	Extended self-refresh temperature range

Bit 6 – ASR Auto Self-Refresh

When enabled (‘1’), SDRAM automatically provides self-refresh power management functions for all supported operating temperature values.

Otherwise, the SRT bit must be programmed to indicate the temperature range.

Bits 5:3 – CWL[2:0] CAS Write Latency

The delay, in clock cycles, between when the SDRAM registers a write command to when write data is available. Valid values are as follows. All other settings are reserved and must not be used.

Value	Description
0	5 (DDR_CLK period = 2.5 ns)
1	6 (2.5 ns >DDR_CLK period = 1.875 ns)
2	7 (1.875 ns > DDR_CLK period = 1.5 ns)
3	8 (1.5 ns > DDR_CLK period = 1.25 ns)

Bits 2:0 – PASR[2:0] Partial Array Self Refresh

Specifies that data located in areas of the array beyond the specified location will be lost if self-refresh is entered.

Value	Description
	Valid settings for 4 banks:
0	Full array
1	Half array (DDR_BA[1:0] = 00 & 01)
2	Quarter array (DDR_BA[1:0] = 00)
3	Not defined
4	3/4 array (DDR_BA[1:0] = 01, 10, & 11)
5	Half array (DDR_BA[1:0] = 10 & 11)
6	Quarter array (DDR_BA[1:0] = 11)
7	Not defined
	Valid settings for 8 banks:
0	Full array
1	Half array (DDR_BA[2:0] = 000, 001, 010 & 011)
2	Quarter array (DDR_BA[2:0] = 000, 001)
3	1/8 array (DDR_BA[2:0] = 000)
4	3/4 array (DDR_BA[2:0] = 010, 011, 100, 101, 110 & 111)
5	Half array (DDR_BA[2:0] = 100, 101, 110 & 111)
6	Quarter array (DDR_BA[2:0] = 110 & 111)
7	1/8 array (DDR_BA[2:0] 111)

Name:	DDR3PHY_MR2_DDR3
Offset:	0x48
Reset:	0x00000000
Property:	Read/Write