18.4.57 DDR3PHY Fail Word 0
Register
| Name: | DDR3PHY_BISTFWR0 |
| Offset: | 0x13C |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | ODTWEBS | | | | CSWEBS | |
| Access | | | | R/W | | | | R/W | |
| Reset | | | | 0 | | | | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | CKEWEBS | WEWEBS | BAWEBS[2:0] | |
| Access | | | | R/W | R/W | R/W | R/W | R/W | |
| Reset | | | | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | AWEBS[15:8] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | AWEBS[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 28 – ODTWEBS DDR_ODT Word Error
Bit Status
Bit status during a word error
for DDR_ODT.
Bit 24 – CSWEBS DDR_CSN Word Error
Bit Status
Bit status during a word error
for DDR_CSN.
Bit 20 – CKEWEBS DDR_CKE Word Error
Bit Status
Bit status during a word error
for DDR_CKE.
Bit 19 – WEWEBS DDR_WEN Word Error
Bit Status
Bit status during a word error
for DDR_WEN.
Bits 18:16 – BAWEBS[2:0] DDR_BA Word Error Bit
Status
Bit status during a word error
for each DDR_BA[2:0].
Bits 15:0 – AWEBS[15:0] DDR_A Word Error
Bit Status
Bit status during a word error
for each DDR_A[15:0].
