18.4.27 DDR3PHY Mode Register 3 (MR3) (DDR2 Mode)Name: DDR3PHY_MR3_EMR3_DDR2Offset: 0x4CReset: 0x00000000Property: Read/WriteBit 3130292827262524 Access Reset Bit 2322212019181716 Access Reset Bit 15141312111098 RSVD[15:8] Access R/WR/WR/WR/WR/WR/WR/WR/W Reset 00000000 Bit 76543210 RSVD[7:0] Access R/WR/WR/WR/WR/WR/WR/WR/W Reset 00000000 Bits 15:0 – RSVD[15:0] ReservedThese are JEDEC reserved bits and are recommended by JEDEC to be programmed to ‘0’.
Bit 3130292827262524 Access Reset Bit 2322212019181716 Access Reset Bit 15141312111098 RSVD[15:8] Access R/WR/WR/WR/WR/WR/WR/WR/W Reset 00000000 Bit 76543210 RSVD[7:0] Access R/WR/WR/WR/WR/WR/WR/WR/W Reset 00000000
Bits 15:0 – RSVD[15:0] ReservedThese are JEDEC reserved bits and are recommended by JEDEC to be programmed to ‘0’.