18.4.12 DDR3PHY DRAM Configuration Register


Bit	31	30	29	28	27	26	25	24
				DDR2T
Access				R/W
Reset				0


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
							DDRTYPE[1:0]
Access							R/W	R/W
Reset							0	0


Bit	7	6	5	4	3	2	1	0
	MPRDQ	PDQ[2:0]			DDR8BNK	DDRMD[2:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	1	0	1	1

Bit 28 – DDR2T DDR 2T Timing

If set, indicates that 2T timing must be used. 2T timing holds the address and command bus valid for 2 clock cycles.

Bits 9:8 – DDRTYPE[1:0] LPDDR2 Type

Selects the LPDDR2 type, when DDRMD[2:0]=4 in this register.

Value	Description
0	LPDDR2-S4
1	LPDDR2-S2

Bit 7 – MPRDQ Multi-Purpose Register (MPR) DDR_D (DDR3 Only)

Specifies the value that is driven on non-primary DDR_D pins during MPR reads.

Value	Description
0	Primary DDR_D drives out the data from MPR (0-1-0-1), non-primary DQs drive ‘0’.
1	Primary DDR_D and non-primary DDR_Dx drive the same data from MPR (0-1-0-1).

Bits 6:4 – PDQ[2:0] Primary DDR_D (DDR3 Only)

Specifies the DDR_D pin in a byte that is designated as a primary pin for DDR3 Multi-Purpose register (MPR) reads. Valid values are 0 to 7 for DDR_D0 to DDR_D7, respectively.

Bit 3 – DDR8BNK DDR 8-Bank

If set, indicates that the SDRAM used has 8 banks. t_RPA = t_RP+1 and t_FAW are used for 8-bank DRAMs, other t_RPA = t_RP and no t_FAW is used. Note that a setting of 1 for DRAMs that have fewer than 8 banks still results in correct functionality but less tight DRAM command spacing for the parameters described here.

Bits 2:0 – DDRMD[2:0] DDR Mode

SDRAM DDR mode.

Value	Description
1	Reserved
2	DDR 2
3	DDR 3
4	LPDDR2 (Mobile DDR2)
5	LPDDR3 (Mobile DDR3)

Name:	DDR3PHY_DCR
Offset:	0x30
Reset:	0x0000000B
Property:	Read/Write