18.4.61 DDR3PHY ZQ Status Register 0

Name:	DDR3PHY_ZQ0SR0
Offset:	0x188
Reset:	0x8006314A
Property:	Read-only


Bit	31	30	29	28	27	26	25	24
	ZDONE	ZERR			ZCTRL[27:24]
Access	R/W	R/W			R/W	R/W	R/W	R/W
Reset	1	0			0	0	0	0


Bit	23	22	21	20	19	18	17	16
	ZCTRL[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	1	1	0


Bit	15	14	13	12	11	10	9	8
	ZCTRL[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	1	1	0	0	0	1


Bit	7	6	5	4	3	2	1	0
	ZCTRL[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	1	0	0	1	0	1	0

Bit 31 – ZDONE Impedance Calibration Done

Indicates that impedance calibration has completed.

Bit 30 – ZERR Impedance Calibration Error

If set, indicates that there was an error during impedance calibration.

Bits 27:0 – ZCTRL[27:0] Impedance Control

Current value of impedance control. Field mapping is as follows:


[27:20]	Reserved, returns zeros on reads
[19:15]	Pull-up on-die termination impedance select
[14:10]	Pull-down on-die termination impedance select
[9:5]	Pull-up output impedance select
[4:0]	Pull-down output impedance select

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