18.4.16 DDR3PHY Mode Register 0 (MR0) (DDR3 Mode)


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
				PD	WR[2:0]			DR
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	1	0	1	0


Bit	7	6	5	4	3	2	1	0
	TM	CL3	CL2	CL1	BT	CL0	BL[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	1	0	1	0	0	0	1

Bit 12 – PD Power-Down Control

Controls the exit time for Power-Down modes. Refer to the SDRAM memory device data sheet for details on Power-Down modes.

Value	Description
0	Slow exit (DLL off)
1	Fast exit (DLL on)

Bits 11:9 – WR[2:0] Write Recovery

This is the value of the write recovery in clock cycles. It is calculated by dividing the data sheet write recovery time, t_WR (ns) by the data sheet DDR clock period (ns) and rounding up a non-integer value to the next integer.

Note: t_WR (ns) is the time from the first SDRAM positive clock edge after the last data-in pair of a write command, to when a precharge of the same bank can be issued.

Valid values are as follows. All other settings are reserved and must not be used.

Value	Description
1	5
2	6
3	7
4	8
5	10
6	12

Bit 8 – DR DLL Reset

Writing a ‘1’ to this bit resets the SDRAM DLL. This bit is self-clearing, i.e. it returns back to ‘0’ after the DLL reset has been issued.

Bit 7 – TM Operating Mode

Value	Description
0	Normal operating mode
1	Test mode. Test mode is reserved for the manufacturer and must not be used.

Bit 6 – CL3 CAS Latency

The delay, in clock cycles, between when the SDRAM registers a read command to when data is available.

CL3, CL2, CL1, CL0= MR0 [6:4,2]

Valid values are as follows. All other settings are reserved and must not be used.

Value	Description
2	5
4	6
6	7
8	8
10	9
12	10
14	11

Bit 5 – CL2 CAS Latency

See CL3.

CL = MR0 [6:4, 2]

Bit 4 – CL1 CAS Latency

See CL3.

CL = MR0 [6:4, 2]

Bit 3 – BT Burst Type

Value	Description
0	Sequential burst
1	Interleaved burst

Bit 2 – CL0 CAS Latency

See CL3.

CL = MR0 [6:4, 2]

Bits 1:0 – BL[1:0] Burst Length

Determines the maximum number of column locations that can be accessed during a given read or write command. Valid values are as follows.

Value	Description
0	8 (fixed)
1	4 or 8 (on the fly)
2	4 (fixed)
3	Reserved

Name:	DDR3PHY_MR0_DDR3
Offset:	0x40
Reset:	0x00000294
Property:	Read/Write