18.4.7 DDR3PHY PHY Timing Register 1
| Name: | DDR3PHY_PTR1 |
| Offset: | 0x1C |
| Reset: | 0x0604111D |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TDINIT1[7:5] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 1 | 1 | 0 | ||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TDINIT1[4:0] | TDINIT0[18:16] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TDINIT0[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TDINIT0[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | |
Bits 26:19 – TDINIT1[7:0] DRAM Initialization Time 1
DDR3 = DDR_CKE high time to first command (tRFC +10 ns or 5 DDR_CLK periods, whichever value is larger)
DDR2 = DDR_CKE high time to first command (400 ns)
LPDDR2 = DDR_CKE low time with power and clock stable (100 ns)
LPDDR3 = CKE low time with power and clock stable (100 ns)
Default value corresponds to DDR3 360 ns at 533 MHz
Bits 18:0 – TDINIT0[18:0] DRAM Initialization Time 0
DDR3 = DDR_CKE low time with power and clock stable (500 µs)
DDR2 = DDR_CKE low time with power and clock stable (200 µs)
LPDDR2 = DDR_CKE high time to first command (200 µs)
LPDDR3 = DDR_CKE high time to first command (200 µs)
Default value corresponds to DDR3 500 µs at 533 MHz.