18.4.40 DDR3PHY DCU Status Register 0
| Name: | DDR3PHY_DCUSR0 |
| Offset: | 0xD8 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | CFULL | CFAIL | RDONE | |
| Access | | | | | | R/W | R/W | R/W | |
| Reset | | | | | | 0 | 0 | 0 | |
Bit 2 – CFULL Capture Full
If set, indicates that the
capture cache is full.
Bit 1 – CFAIL Capture Fail
If set, indicates that at least
one read data word has failed.
Bit 0 – RDONE Run Done
If set, indicates that the DCU
has finished executing the commands in the command cache. This bit is also set to
indicate that a STOP command has successfully been executed and command execution
has stopped.
