18.4.14 DDR3PHY DRAM Timing Parameter Register 1


Bit	31	30	29	28	27	26	25	24
			TDQSCKmax[2:0]			TDQSCKmin[2:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	1	0	0	1


Bit	23	22	21	20	19	18	17	16
	TRFC[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	0	0	0	0	0	1	1


Bit	15	14	13	12	11	10	9	8
					TRTODT	TMOD[1:0]		TFAW[5]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
	TFAW[4:0]					TRTW	TAOND/ TAOFD[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	0	0	1	0	0	0	0

Bits 29:27 – TDQSCKmax[2:0] Maximum DDR_DQS Output Access Time from DDR_CLK/DDR_CLKN (LPDDR2 only)

Used for implementing read-to-write spacing. Valid values are 1 to 7.

Bits 26:24 – TDQSCKmin[2:0] DQS Output Access Time from DDR_CLK/DDR_CLKN (LPDDR2/3 only)

Used for computing the read latency. Valid values are 0 to 7. This value is derived from the corresponding parameter in the SDRAM memory device data sheet divided by the clock cycle time without rounding up. The fractional remainder is automatically adjusted for by data training in quarter clock cycle units. If data training is not performed, then this fractional remainder must be converted to quarter clock cycle units and the gating registers (DDR3PHY_DXnDQSTR) adjusted accordingly.

Bits 23:16 – TRFC[7:0] Refresh-to-Refresh

Indicates the minimum time, in clock cycles, between two refresh commands or between a refresh and an active command. This is derived from the minimum refresh interval from the datasheet, t_RFC(min), divided by the clock cycle time. The default number of clock cycles is for the largest JEDEC t_RFC(min parameter value supported).

Bit 11 – TRTODT Read to ODT Delay (DDR3 only)

Specifies whether ODT can be enabled immediately after the read post-amble or whether one clock delay has to be added.

If TRTODT is set to 1, then the read-to-write latency is increased by 1 if ODT is enabled.

Value	Description
0	ODT may be turned on immediately after read post-amble
1	ODT may not be turned on until one clock delay after the read post-amble

Bits 10:9 – TMOD[1:0] Load Mode Update Delay (DDR3 only)

The minimum time between a load Mode register command and a non-load Mode register command.

Value	Description
0	12
1	13
2	14
3	15

Bits 8:3 – TFAW[5:0] 4-bank Activate Period

No more than four bank-activate commands may be issued in a given TFAW period. Only applies to 8-bank devices. Valid values are 2 to 31.

Bit 2 – TRTW Read to Write Command Delay

Allows the user to increase the delay between issuing Write commands to the SDRAM when preceded by Read commands. This provides an option to increase bus turnaround margin for high-frequency systems.

Value	Description
0	Standard bus turn around delay
1	Adds one clock to standard bus turn around delay

Bits 1:0 – TAOND/ TAOFD[1:0] ODT Turn-On/Turn-Off Delays (DDR2 only)

The delays are in clock cycles.

Most DDR2 devices utilize a fixed value of 2/2.5. For non-standard SDRAMs, the user must ensure that the operational write latency is always greater than or equal to the ODT turn-on delay. For example, a DDR2 SDRAM with CAS latency set to 3 and CAS additive latency set to 0 has a write latency of 2. Thus 2/2.5 can be used, but not 3/3.5 or higher.

Value	Description
0	2/2.5
1	3/3.5
2	4/4.5
3	5/5.5

Name:	DDR3PHY_DTPR1
Offset:	0x38
Reset:	0x09830090
Property:	Read/Write