18.4.53 DDR3PHY BIST Bit Error 0 Register

Name:	DDR3PHY_BISTBER0
Offset:	0x12C
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	ABER[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	ABER[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	ABER[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ABER[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 31:0 – ABER[31:0] Address Bit Error

Each group of two bits indicates the bit error count on each DDR_A[15:0]. ABER[1:0] is the error count for DDR_A[0], ABER[3:2] for DDR_A[1], and so on.