18.4.65 DDR3PHY Data Byte General Status Register 1

Name:	DDR3PHY_DXxGSR1
Offset:	0x01C8 + x*0x40 [x=0..1]
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
			RVPASS[1:0]					RVIERR
Access			R/W	R/W				R/W
Reset			0	0				0


Bit	15	14	13	12	11	10	9	8
				RVERR
Access				R/W
Reset				0


Bit	7	6	5	4	3	2	1	0
			DQSDFT[1:0]					DFTERR
Access			R/W	R/W				R/W
Reset			0	0				0

Bits 21:20 – RVPASS[1:0] Read Valid Training Pass Count

The number of passing configurations during read valid training.

Bit 16 – RVIERR Read Valid Training Intermittent Error

If set, indicates that there was an intermittent error during read valid training of the byte, such as a pass was followed by a fail then followed by another pass.

Bit 12 – RVERR Read Valid Training Error

If set, indicates that a valid read valid placement could not be found during read valid training of the byte.

Bits 5:4 – DQSDFT[1:0] DQS Drift

Used to report the drift on the read data strobe of the data byte.

Value	Description
0	No drift
1	90° drift
2	180° drift
3	270° drift or more

Bit 0 – DFTERR DQS Drift Error

If set, indicates that the byte read data strobe has drifted by more than or equal to the drift limit set in DDR3PHY_PGCR.