18.4.8 DDR3PHY PHY Timing Register 2
| Name: | DDR3PHY_PTR2 |
| Offset: | 0x20 |
| Reset: | 0x042DA072 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| TDINIT3[9:7] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 1 | 0 | 0 | ||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TDINIT3[6:0] | TDINIT2[16] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TDINIT2[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TDINIT2[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | |
Bits 26:17 – TDINIT3[9:0] DRAM Initialization Time 3
LPDDR2 = Time from DDR_ZQ initialization command to first command (1 µs)
LPDDR3 = Time from DDR_ZQ initialization command to first command (1 µs)
Default value corresponds to the LPDDR2/3 1 µs at 533 MHz.
Bits 16:0 – TDINIT2[16:0] DRAM Initialization Time 2
DDR3 = Reset low time (200 µs on power-up or 100 ns after power-up)
LPDDR2 = Time from reset command to end of auto-initialization (11 µs)
LPDDR3 = Time from reset command to end of auto-initialization (11 µs)
Default value corresponds to DDR3 200 µs at 533 MHz.