18.4.37 DDR3PHY DCU Loop Register
| Name: | DDR3PHY_DCULR |
| Offset: | 0xCC |
| Reset: | 0xF0000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | XLEADDR[3:0] | | | | | |
| Access | R/W | R/W | R/W | R/W | | | | | |
| Reset | 1 | 1 | 1 | 1 | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | IDA | LINF | |
| Access | | | | | | | R/W | R/W | |
| Reset | | | | | | | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | LCNT[7:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | LEADDR[3:0] | LSADDR[3:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:28 – XLEADDR[3:0] Expected Data Loop End Address
The last expected data cache
word address that contains valid expected data. Expected data must looped between 0
and this address.
Bit 17 – IDA Increment DRAM Address
If set, indicates that DRAM
addresses must be incremented every time a DRAM read/write command inside the loop
is executed.
Bit 16 – LINF Loop Infinite
If set, indicates that the loop
must be executed indefinitely until stopped by the STOP command. Otherwise the loop
is executed LCNT times.
Bits 15:8 – LCNT[7:0] Loop Count
The number of times that the
loop must be executed if LINF is not set.
Bits 7:4 – LEADDR[3:0] Loop End Address
Command cache word address where
the loop ends.
Bits 3:0 – LSADDR[3:0] Loop Start Address
Command cache word address where
the loop starts.
