18.4.26 DDR3PHY Mode Register 3 (MR3) (DDR3 Mode)

Name:	DDR3PHY_MR3_DDR3
Offset:	0x4C
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	RSVD[12:5]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	RSVD[4:0]					MPR	MPRLOC[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:3 – RSVD[12:0] Reserved

These are JEDEC reserved bits and are recommended by JEDEC to be programmed to ‘0’

Bit 2 – MPR Multi-Purpose Register Enable

If set, enables that read data comes from the DDR3 Multi-Purpose register (MPR). Otherwise read data come from the DRAM array. Refer to the memory vendor data sheet for details.

Bits 1:0 – MPRLOC[1:0] Multi-Purpose Register (MPR) Location

Selects DDR3 Multi-Purpose register (MPR) data location. Valid value is:

00 = Predefined pattern for system calibration

All other settings are reserved and must not be used.