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18.4.60 DDR3PHY ZQ Impedance Control
Register 1 Name: DDR3PHY_ZQ0CR1 Offset: 0x184 Reset: 0x0000007B Property: Read/Write
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 Access Reset
Bit 15 14 13 12 11 10 9 8 Access Reset
Bit 7 6 5 4 3 2 1 0 ZPROG[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 1 1 1 1 0 1 1
Bits 7:0 – ZPROG[7:0] Impedance Divide
Ratio
Selects the external
resistor divide ratio to be used to set the output impedance and the on-die
termination.
ZPROG[3:0] (decimal)
RZQ =240±1% Programmed Zo
(Ohms)
DDR3/DDR3L
DDR2
LPDDR2/3
5
–
–
80
7
–
–
60
9
–
–
48
11
40
40
40
13
34
–
34
–
–
18(1)
–
ZPROG[7:4] (decimal)
Programmed ODT (Ohms)
DDR3/DDR3L
DDR2
1
120
150
4
–
75
5
60
–
6
–
50
8
40
–
Note:
To program 18 ohms, see Custom
Calibration .
Using different RZQ values
in the range of 240–300 ohms, different impedance values may be obtained.
ODT and driver output impedance are calibrated independently.
For a detailed calibration procedure,
see Impedance
Calibration .
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
