18.4.51 DDR3PHY General Status
Register
| Name: | DDR3PHY_BISTGSR |
| Offset: | 0x124 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | CASBER[1:0] | RASBER[1:0] | DMBER[3:0] | |
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | BDXERR | BACERR | BDONE | |
| Access | | | | | | R/W | R/W | R/W | |
| Reset | | | | | | 0 | 0 | 0 | |
Bits 31:30 – CASBER[1:0] DDR_CASN Bit
Error
Indicates the number of bit errors
on DDR_CASN.
Bits 29:28 – RASBER[1:0] DDR_RASN Bit
Error
Indicates the number of bit errors
on DDR_RASN.
Bits 27:24 – DMBER[3:0] DDR_DQM Bit
Error
Indicates the number of bit errors
on data mask (DDR_DQM) bit. DMBER[1:0] are for the first DDR_DQM beat, and DMBER[3:2] are
for the second DDR_DQM beat.
Bit 2 – BDXERR BIST Data Error
If set, indicates that there is a
data comparison error in the byte lane.
Bit 1 – BACERR BIST Address/Command Error
If set, indicates that there is a
data comparison error in the address/command lane.
Bit 0 – BDONE BIST
Done
If set, indicates that the BIST
has finished executing. This bit is reset to zero when BIST is
triggered.
