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Libero IDE v9.x
Libero IDE v9.x
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  2. 13 Libero IDE
  3. 13.33 Project Manager Tcl Commands
  4. 13.33.69 export
  5. 13.33.69.3 export (Designer Block support for IGLOO, Fusion, ProASIC3, Axcelerator, and RTAX families)
  6. 13.33.69.3.36 Example
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  • 1 FlashROM, Analog System Builder, and Flash Memory System Builder
  • 2 Analog System Builder, FlashROM and Flash Memory System Builder
  • 3 ChipEditor
  • 4 Designer Documentation Catalog
  • 5 Libero IDE
  • 6 Design Constraints for Software
  • 7 Innoveda eProduct Designer Interface Guide - UNIX
  • 8 Innoveda eProduct Designer Interface Guide – Windows
  • 9 FlashPro for Software
  • 10 SmartGen Cores Reference
  • 11 HDL Coding Style
  • 12 Libero IDE Documentation Catalog
  • 13 Libero IDE
    • 13 What's New in Libero IDE v9.1
    • 13.1 Supported Families
    • 13.2 Project Management
    • 13.3 Project Files
    • 13.4 Project Options
    • 13.5 Settings
    • 13.6 Preferences
    • 13.7 Project Manager Interface
    • 13.8 Designing with Designer Block Components
    • 13.9 Creating a Designer Block Component in Libero IDE
    • 13.10 Creating a Designer Block Component in Designer
    • 13.11 Instantiating a Designer Block Component in Designer
    • 13.12 SmartDesign
    • 13.13 Getting Started with SmartDesign
    • 13.14 SmartDesign User Interface
    • 13.15 Canvas View
    • 13.16 Grid
    • 13.17 Instance-Instance View
    • 13.18 Schematic View
    • 13.19 Creating a SmartDesign
    • 13.20 Connecting Instances
    • 13.21 Bus Interfaces
    • 13.22 Incremental Design
    • 13.23 Reference
    • 13.24 Welcome to Designer
    • 13.25 Device Selection
    • 13.26 Design Constraints
    • 13.27 Families Supported
    • 13.28 Entering Constraints
    • 13.29 Running Layout
    • 13.30 Device Programming
    • 13.31 Generating Programming Files
    • 13.32 TCL Command Reference
    • 13.33 Project Manager Tcl Commands
      • 13.33.1 add_file_to_library
      • 13.33.2 add_library
      • 13.33.3 add_modelsim_path
      • 13.33.4 add_profile
      • 13.33.5 associate_stimulus
      • 13.33.6 change_link_source
      • 13.33.7 check_hdl
      • 13.33.8 close_project
      • 13.33.9 check_schematic
      • 13.33.10 create_links
      • 13.33.11 create_symbol
      • 13.33.12 delete_files
      • 13.33.13 edit_profile
      • 13.33.14 export_as_link
      • 13.33.15 export_io_constraints_from_adb
      • 13.33.16 export_profiles
      • 13.33.17 generate_ba_files
      • 13.33.18 generate_hdl_from_schematic
      • 13.33.19 generate_hdl_netlist
      • 13.33.20 import_files (Libero IDE)
      • 13.33.21 new_project
      • 13.33.22 open_project
      • 13.33.23 organize_cdbs
      • 13.33.24 Arguments
      • 13.33.25 organize_sources
      • 13.33.26 project_settings
      • 13.33.27 refresh
      • 13.33.28 remove_core
      • 13.33.29 remove_library
      • 13.33.30 remove_profile
      • 13.33.31 rename_library
      • 13.33.32 rollback_constraints_from_adb
      • 13.33.33 run_designer
      • 13.33.34 run_drc
      • 13.33.35 run_simulation
      • 13.33.36 run_synthesis
      • 13.33.37 save_log
      • 13.33.38 save_project
      • 13.33.39 save_project_as
      • 13.33.40 select_profile
      • 13.33.41 set_actel_lib_options
      • 13.33.42 set_device (Project Manager)
      • 13.33.43 set_modelsim_options
      • 13.33.44 set_option
      • 13.33.45 set_user_lib_options
      • 13.33.46 set_root
      • 13.33.47 synplify
      • 13.33.48 _pro
      • 13.33.49 unlink
      • 13.33.50 use_file
      • 13.33.51 use_source_file
      • 13.33.52 About Designer Tcl Commands
      • 13.33.53 Tcl command documentation conventions
      • 13.33.54 add_probe
      • 13.33.55 all_inputs
      • 13.33.56 all_outputs
      • 13.33.57 all_registers
      • 13.33.58 are_all_source_files_current
      • 13.33.59 backannotate
      • 13.33.60 check_timing_constraints
      • 13.33.61 clone_scenario
      • 13.33.62 close_design
      • 13.33.63 compile
      • 13.33.64 create_clock
      • 13.33.65 create_generated_clock
      • 13.33.66 create_scenario
      • 13.33.67 delete_probe
      • 13.33.68 delete_scenario
      • 13.33.69 export
        • 13.33.69.1 export (IGLOO, ProASIC3, SmartFusion and Fusion)
        • 13.33.69.2 export (ProASICPLUS, ProASIC, Axcelerator, MX, eX, and SX/SX-A)
        • 13.33.69.3 export (Designer Block support for IGLOO, Fusion, ProASIC3, Axcelerator, and RTAX families)
          • 13.33.69.3.1 Arguments
          • 13.33.69.3.2 Supported Families
          • 13.33.69.3.3 Exceptions
          • 13.33.69.3.4 Example
          • 13.33.69.3.5 import_source
          • 13.33.69.3.6 Supported Families
          • 13.33.69.3.7 Exceptions
          • 13.33.69.3.8 Examples
          • 13.33.69.3.9 Arguments
          • 13.33.69.3.10 Supported Families
          • 13.33.69.3.11 Exceptions
          • 13.33.69.3.12 Example
          • 13.33.69.3.13 Arguments
          • 13.33.69.3.14 Supported Families
          • 13.33.69.3.15 Exceptions
          • 13.33.69.3.16 Example
          • 13.33.69.3.17 Arguments
          • 13.33.69.3.18 Supported Families
          • 13.33.69.3.19 Exceptions
          • 13.33.69.3.20 Example
          • 13.33.69.3.21 Arguments
          • 13.33.69.3.22 Supported Families
          • 13.33.69.3.23 Exceptions
          • 13.33.69.3.24 Example
          • 13.33.69.3.25 Arguments
          • 13.33.69.3.26 Supported Families
          • 13.33.69.3.27 Exceptions
          • 13.33.69.3.28 Example
          • 13.33.69.3.29 Arguments
          • 13.33.69.3.30 Supported Families
          • 13.33.69.3.31 Exceptions
          • 13.33.69.3.32 Example
          • 13.33.69.3.33 Arguments
          • 13.33.69.3.34 Supported Families
          • 13.33.69.3.35 Exceptions
          • 13.33.69.3.36 Example
          • 13.33.69.3.37 Arguments
          • 13.33.69.3.38 Supported Family
          • 13.33.69.3.39 Description
          • 13.33.69.3.40 Exceptions
          • 13.33.69.3.41 Example
          • 13.33.69.3.42 Arguments
          • 13.33.69.3.43 Supported Family
          • 13.33.69.3.44 Description
          • 13.33.69.3.45 Exceptions
          • 13.33.69.3.46 Example
          • 13.33.69.3.47 Arguments
          • 13.33.69.3.48 Supported Family
          • 13.33.69.3.49 Description
          • 13.33.69.3.50 Exceptions
          • 13.33.69.3.51 Example
          • 13.33.69.3.52 Arguments
          • 13.33.69.3.53 Supported Families
          • 13.33.69.3.54 Exceptions
          • 13.33.69.3.55 Example
      • 13.33.70 generate_probes
      • 13.33.71 get_cells
      • 13.33.72 get_clocks pattern
      • 13.33.73 get_current_scenario
      • 13.33.74 get_defvar
      • 13.33.75 get_design_filename
      • 13.33.76 get_design_info
      • 13.33.77 ***
      • 13.33.78 get_out_of_date_files
      • 13.33.79 get_pins
      • 13.33.80 get_ports
      • 13.33.81 import_aux
      • 13.33.82 layout - IGLOO, ProASIC3, SmartFusion and Fusion
      • 13.33.83 layout - Advanced Options for IGLOO, ProASIC3, SmartFusion and Fusion
      • 13.33.84 layout - ProASIC and ProASICPLUS
      • 13.33.85 layout - Advanced Layout Options for ProASIC and ProASICPLUS
      • 13.33.86 layout - Axcelerator
      • 13.33.87 layout - Advanced Options for Axcelerator
      • 13.33.88 layout - SX-A, eX, and SX
      • 13.33.89 layout - Advanced Options for SX-A, eX, and SX
      • 13.33.90 layout - MX, DX, ACT
      • 13.33.91 layout - Advanced Options for MX, DX, ACT
      • 13.33.92 list_clocks
      • 13.33.93 list_clock_latencies
      • 13.33.94 list_clock_uncertainties
      • 13.33.95 list_disable_timings
      • 13.33.96 list_false_paths
      • 13.33.97 list_generated_clocks
      • 13.33.98 list_input_delays
      • 13.33.99 list_max_delays
      • 13.33.100 list_min_delays
      • 13.33.101 list_multicycle_paths
      • 13.33.102 list_objects
      • 13.33.103 list_output_delays
      • 13.33.104 list_scenarios
      • 13.33.105 LOGFILE
      • 13.33.106 new_design
      • 13.33.107 open_design
      • 13.33.108 pin_assign
      • 13.33.109 pin_commit
      • 13.33.110 pin_fix
      • 13.33.111 pin_fix_all
      • 13.33.112 pin_unassign
      • 13.33.113 pin_unassign_all
      • 13.33.114 pin_unfix
      • 13.33.115 report (Timing violations) using SmartTime
      • 13.33.116 remove_clock
      • 13.33.117 remove_clock_latency
      • 13.33.118 remove_clock_uncertainty
      • 13.33.119 remove_disable_timing
      • 13.33.120 remove_false_path
      • 13.33.121 remove_generated_clock
      • 13.33.122 remove_input_delay
      • 13.33.123 remove_library
      • 13.33.124 remove_max_delay
      • 13.33.125 remove_min_delay
      • 13.33.126 remove_multicycle_path
      • 13.33.127 remove_output_delay
      • 13.33.128 rename_library
      • 13.33.129 rename_scenario
      • 13.33.130 report
      • 13.33.131 save_design
      • 13.33.132 set_clock_latency
      • 13.33.133 set_clock_uncertainty
      • 13.33.134 set_current_scenario
      • 13.33.135 set_defvar
      • 13.33.136 Arguments
      • 13.33.137 set_design
      • 13.33.138 set_disable_timing
      • 13.33.139 set_false_path
      • 13.33.140 set_input_delay
      • 13.33.141 set_max_delay
      • 13.33.142 set_min_delay
      • 13.33.143 set_multicycle_path
      • 13.33.144 set_output_delay
      • 13.33.145 smartpower_add_new_custom_mode
      • 13.33.146 smartpower_add_new_scenario
      • 13.33.147 smartpower_add_pin_in_domain
      • 13.33.148 smartpower_change_clock_statistics
      • 13.33.149 smartpower_change_setofpin_statistics
      • 13.33.150 smartpower_commit
      • 13.33.151 smartpower_create_domain
      • 13.33.152 smartpower_edit_custom_mode
      • 13.33.153 smartpower_edit_scenario
      • 13.33.154 smartpower_init_do
      • 13.33.155 smartpower_init_set_clocks_options
      • 13.33.156 smartpower_init_set_combinational_options
      • 13.33.157 smartpower_init_setofpins_values
      • 13.33.158 smartpower_init_set_enables_options
      • 13.33.159 smartpower_init_set_othersets_options
      • 13.33.160 smartpower_init_set_primaryinputs_options
      • 13.33.161 smartpower_init_set_registers_options
      • 13.33.162 smartpower_init_set_set_reset_options
      • 13.33.163 smartpower_remove_all_annotations
      • 13.33.164 smartpower_remove_custom_mode
      • 13.33.165 smartpower_remove_domain
      • 13.33.166 smartpower_remove_pin_enable_rate
      • 13.33.167 smartpower_remove_pin_frequency
      • 13.33.168 smartpower_remove_pin_of_domain
      • 13.33.169 smartpower_remove_pin_probability
      • 13.33.170 smartpower_remove_scenario
      • 13.33.171 smartpower_remove_vcd
      • 13.33.172 smartpower_restore
      • 13.33.173 smartpower_set_battery_capacity
      • 13.33.174 smartpower_set_cooling
      • 13.33.175 smartpower_set_mode_for_analysis
      • 13.33.176 smartpower_set_operating_condition
      • 13.33.177 smartpower_set_pin_enable_rate
      • 13.33.178 smartpower_set_pin_frequency
      • 13.33.179 smartpower_set_preferences
      • 13.33.180 smartpower_set_scenario_for_analysis
      • 13.33.181 smartpower_set_temperature_opcond
      • 13.33.182 smartpower_set_thermalmode
      • 13.33.183 smartpower_set_voltage_opcond
      • 13.33.184 smartpower_temperature_opcond_set_design_wide
      • 13.33.185 smartpower_temperature_opcond_set_mode_specific
      • 13.33.186 smartpower_voltage_opcond_set_design_wide
      • 13.33.187 smartpower_voltage_opcond_set_mode_specific
      • 13.33.188 st_commit
      • 13.33.189 st_create_set
      • 13.33.190 st_edit_set
      • 13.33.191 ***
      • 13.33.192 st_list_paths
      • 13.33.193 st_remove_set
      • 13.33.194 st_restore
      • 13.33.195 st_set_options
      • 13.33.196 timer_add_clock_exception
      • 13.33.197 timer_add_pass
      • 13.33.198 timer_add_stop
      • 13.33.199 timer_commit
      • 13.33.200 timer_get_path
      • 13.33.201 timer_get_clock_actuals
      • 13.33.202 timer_get_clock_constraints
      • 13.33.203 timer_get_maxdelay
      • 13.33.204 timer_get_path_constraints
      • 13.33.205 timer_remove_clock_exception
      • 13.33.206 timer_remove_pass
      • 13.33.207 timer_remove_stop
      • 13.33.208 timer_restore
      • 13.33.209 timer_setenv_clock_freq
      • 13.33.210 timer_setenv_clock_period
      • 13.33.211 timer_set_maxdelay
      • 13.33.212 timer_remove_all_constraints
      • 13.33.213 use_file
      • 13.33.214 use_source_file
      • 13.33.215 Add or Edit Profile Dialog Box
      • 13.33.216 Project Manager - Cores Dialog Box (Advanced Download Mode
      • 13.33.217 Catalog Options Dialog Box
      • 13.33.218 CDB File Organization Dialog Box
      • 13.33.219 Change All Links Dialog Box
      • 13.33.220 Configure Flow Dialog Box
      • 13.33.221 Convert Project Dialog Box
      • 13.33.222 Export Profiles Dialog Box
      • 13.33.223 Import Files Dialog Box (Project Manager)
      • 13.33.224 New Project Wizard: Add Files
      • 13.33.225 New Project Wizard: Completing
      • 13.33.226 New Project Wizard: Start
      • 13.33.227 New Project Wizard: Select Device
      • 13.33.228 New Project Wizard: Select Integrated Tools
      • 13.33.229 Open Project Dialog Box
      • 13.33.230 Organize Constraints for Synthesis Dialog Box
      • 13.33.231 Organize Stimulus Dialog Box
      • 13.33.232 Page Setup Dialog Box
      • 13.33.233 Profiles Dialog Box
      • 13.33.234 Save Project As Dialog Box
      • 13.33.235 Script Export Options Dialog Box
    • 13.34 Reference
    • 13.35 Dialog Boxes
    • 13.36 Revision History
    • 13 Microchip FPGA Support
    • 13 Microchip Information
  • 14 Antifuse Macro Library Guide for Software
  • 15 MultiView Navigator
  • 16 NetlistViewer (non-MVN)
  • 17 IGLOO, ProASIC3, SmartFusion and Fusion Macro Library for Software
  • 18 ProASIC and ProASIC PLUS Macro Library for Software
  • 19 PinEditor (non-MVN)
  • 20 SmartPower
  • 21 SmartTime
  • 22 Timer
  • 23 VHDL Vital Simulation
  • 24 Verilog Simulation
  • 25 Technical Support
  • 26 About Microchip

13.33.69.3.36 Example

The following code sets the slew for two I/Os.

ioadvisor_set_slew -io{nPWM_out_pad} -io{PWM_out_pad} -slew{high}

See Also ioadvisor_apply_suggestion ioadvisor_commit ioadvisor_restore ioadvisor_restore_initial_value ioadvisor_set_outdrive ioadvisor_set_outputload

is_design_loaded

is_design_loaded

Returns a Boolean value (0 for false, 1 for true) indicating if a design is loaded in the Designer software. True is returned if a design is currently loaded.

Rev: A

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