5.34.130.41 Examples

The following example specifies all paths from clock pins of the registers in clock domain clk1 to data pins of a specific register in clock domain clk2 as false paths:

set_false_path –from [get_clocks {clk1}] –to reg_2:D

The following example specifies all paths through the pin U0/U1:Y to be false:

set_false_path -through U0/U1:Y

set_input_delay

set_input_delay delay_value -clock clock_ref [–max] [–min] [–clock_fall] input_list

Creates an input delay on a port list by defining the arrival time of an input relative to a clock in the current scenario.