24.3.40 Controller Mode SDA Hold
and Mode Switch Delay Timing Register
| Name: | I3CxSDAHLDTIM |
| Offset: | 0x7A90D0 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | SDATXHLD[2:0] | |
| Access | | | | | | R/W | R/W | R/W | |
| Reset | | | | | | 0 | 0 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | SDAPPODDLY[2:0] | |
| Access | | | | | | R/W | R/W | R/W | |
| Reset | | | | | | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | | | SDAODPPDLY[2:0] | |
| Access | | | | | | R/W | R/W | R/W | |
| Reset | | | | | | 0 | 0 | 0 | |
Bits 18:16 – SDATXHLD[2:0]
This field controls
the hold time (in terms of the peripheral clock period) of the transmit data (SDA)
with respect to the SCL edge in FM, FM+, SDR and DDR speed modes of operation. The
valid values are 1 to 7. Others are Reserved.
Bits 10:8 – SDAPPODDLY[2:0]
This field is used to delay
the SDA out with respect to the peripheral clock while switching the transfer from
PP1 (Push-Pull Mode SDA=1) to OD1 (Open-Drain SDA=1). The valid value can range from
0 to 4. Others are Reserved.
Bits 2:0 – SDAODPPDLY[2:0]
This field is used to delay
the peripheral clock with respect to SDA out while switching the transfer from OD1
(Open-Drain Mode SDA=1) to PP1 (Push-Pull Mode SDA=1). The valid values can range
from 0 to 4. Others are Reserved.
