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24.3.34 Controller Mode SCL I3C
Open Drain Timing Register
Note:
The count value takes the
number of peripheral clocks to maintain the I/O SCL High/Low Period
timing.
Name: I3CxSCLODTIM Offset: 0x7A90B4
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 ODHCNT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 1 0 0 0 0
Bit 15 14 13 12 11 10 9 8 Access Reset
Bit 7 6 5 4 3 2 1 0 ODLCNT[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bits 23:16 – ODHCNT[7:0]
I3 C Open-Drain High Count bits(1)
Bits 7:0 – ODLCNT[7:0]
I3 C Open-Drain Low Count bits(1)
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