24.3.20 Target Mode Device Operating Status Register (Target mode only)

Note:
  1. Setting this bit requires a few SCL clocks after the Target has NACKed the read transfer.
  2. This bit is set if the Target terminates a read transfer due to the unavailability of data in the transmit buffer.
Name: I3CxTGTCCCSTAT
Offset: 0x7A9058

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
   FRMERRBUFFNTAVAILDATNTRDYOVFLWERRTGTBUSYUDFLWERR 
Access RRRRRR 
Reset 000000 
Bit 76543210 
 ACTIMOD[1:0]PROTOERR PNDINGINT[3:0] 
Access RRRRRRR 
Reset 0000000 

Bit 13 – FRMERR Frame Error bit

ValueDescription
1 Frame error in HDR-DDR (private write)
0 Cleared when Controller reads status through GETSTATUS CCC

Bit 12 – BUFFNTAVAIL Buffer Not Available bit

ValueDescription
1 Private write request from Controller is NACKed because the RX Buffer does not have the I3C1BUFTHLD [RXSTART] number of empty locations or the Response Buffer is full.
0 Cleared when the Controller reads the status through the GETSTATUS CCC. In SDR mode, it is also cleared upon space becoming available in the buffer and the successful completion of the next write transfer.

Bit 11 – DATNTRDY Data Not Ready bit

ValueDescription
1 Private write request from Controller is NACKed because the Command FIFO is empty, the Transmit FIFO threshold is not met or the Response FIFO is full(1) .
0 Cleared when Controller reads status through GETSTATUS CCC

Bit 10 – OVFLWERR Overflow Error bit

ValueDescription
1 Overflow error condition detected during Controller write transfer.
0 Cleared when the Controller reads status through GETSTATUS CCC.

Bit 9 – TGTBUSY Target Busy bit

ValueDescription
1 Change is made by the current Controller into the MRL register or occurrence of any error.
0 Target application resumes the target operation by setting the I3CxCTRL[RESUME] bit.

Bit 8 – UDFLWERR Underflow Error bit

ValueDescription
1 Underflow Error during private Controller read transfer(2).
0 Cleared when the Controller reads the status through GETSTATUS CCC.

Bits 7:6 – ACTIMOD[1:0] Activity Mode bits

This bit reflects the activity mode of the Target.

Bit 5 – PROTOERR Protocol Error bit

ValueDescription
1 Parity/CRC error during data transfer write.
0 No error.

Bits 3:0 – PNDINGINT[3:0] Pending Interrupt bit

ValueDescription
1 Pending interrupt.
0 No pending interrupt.