24.3.195 I3C Control Register
Note:
- The Fault injection (I3CCON.FLTINJ) must be disabled and re-enabled to capture the new value from the I3CxFLTINJ register.
- Applicable only for Controller mode to enable I2C/SMB2/SMB3 voltage levels.
| Name: | I3CxCON |
| Offset: | 0x7A9570 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| SLPEN | ALTI3C | INTPUR | |||||||
| Access | R | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| TTXDMACHSEL1[3:0] | TTXDMACHSEL0[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | SIDL | FLTINJ | SLWEN | SMB3 | SMB2 | I2C | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TXDMACHSEL[3:0] | RXDMACHSEL[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 29 – SLPEN Sleep Enable bit
| Value | Description |
|---|---|
| 1 | Module operates in Sleep mode. |
| 0 | Module disabled in Sleep mode. |
Bit 26 – ALTI3C Alternate I3C Pin Mapping bit
| Value | Description |
|---|---|
| 1 | Alternate location for I3CSCL/I3CSDA (I3CASCL/I3CASDA). |
| 0 | Default location for I3CSCL/I3CSDA pins. |
Bit 25 – INTPUR Internal Pull-Up Pin Enable bit
| Value | Description |
|---|---|
| 1 | Internal pull-up enabled. |
| 0 | Internal pull-up disabled. |
Bits 23:20 – TTXDMACHSEL1[3:0] Target Transmit DMA Acknowledge Channel “0” Selection bits
| Value | Description |
|---|---|
| 1111 | Check the Channel “15” done acknowledgment state. |
| …. | |
| 0011 | Check the Channel “3” done acknowledgment state. |
| 0010 | Check the Channel “2” done acknowledgment state. |
| 0001 | Check the Channel “1” done acknowledgment state. |
| 0000 | Check the Channel “0” done acknowledgment state. |
Bits 19:16 – TTXDMACHSEL0[3:0] Target Mode Transmit DMA Acknowledge Channel “0” Selection bits
| Value | Description |
|---|---|
| 1111 | Check the Channel “15” done acknowledgment state. |
| …. | |
| 0011 | Check the Channel “3” done acknowledgment state. |
| 0010 | Check the Channel “2” done acknowledgment state. |
| 0001 | Check the Channel “1” done acknowledgment state. |
| 0000 | Check the Channel “0” done acknowledgment state. |
Bit 15 – ON Module Enable bit
| Value | Description |
|---|---|
| 1 | Module enabled. |
| 0 | Module disabled. |
Bit 13 – SIDL Stop in Idle bit
| Value | Description |
|---|---|
| 1 | Module stops operation in Idle mode. |
| 0 | Module continues operation in Idle mode. |
Bit 12 – FLTINJ Fault Injection Sequence Enable bit
| Value | Description |
|---|---|
| 1 | Fault injection is disabled. |
| 0 | Fault injection is enabled when the content of RAM matches ECCFADDR. |
Bit 11 – SLWEN Slew Rate Control Enable bit
| Value | Description |
|---|---|
| 1 | Slew rate control enabled for high-speed mode (400 kHz). |
| 0 | Slew rate control disabled for standard speed mode (disabled for 1 MHz mode). |
Bit 10 – SMB3 SMB3 Enable bit(2)
| Value | Description |
|---|---|
| 1 | Enable SMBus 3.0 bus configuration. |
| 0 | Disable SMBus 3.0 bus configuration. |
Bit 9 – SMB2 SMB2 Enable bit(2)
| Value | Description |
|---|---|
| 1 | Enable SMBus 2.0 bus configuration. |
| 0 | Disable SMBus 2.0 bus configuration. |
Bit 8 – I2C I2C Enable bit(2)
| Value | Description |
|---|---|
| 1 | Enable I2C bus operation. |
| 0 | Disable I2C bus operation. |
Bits 7:4 – TXDMACHSEL[3:0] Transmit DMA Acknowledge Channel Selection bits
| Value | Description |
|---|---|
| 1111 | Check the Channel “15” done acknowledgment state. |
| …. | |
| 0011 | Check the Channel “3” done acknowledgment state. |
| 0010 | Check the Channel “2” done acknowledgment state. |
| 0001 | Check the Channel “1” done acknowledgment state. |
| 0000 | Check the Channel “0” done acknowledgment state. |
Bits 3:0 – RXDMACHSEL[3:0] Receive DMA Acknowledge Channel Selection bits
| Value | Description |
|---|---|
| 1111 | Check the Channel “15” done acknowledgment state. |
| …. | |
| 0011 | Check the Channel “3” done acknowledgment state. |
| 0010 | Check the Channel “2” done acknowledgment state. |
| 0001 | Check the Channel “1” done acknowledgment state. |
| 0000 | Check the Channel “0” done acknowledgment state. |