24.3.196 I3C Pulse Gobbler Register
Note:
- This register setting is required for I2C mode.
- It is the user's responsibility to write to the I3CxPG register before the module is enabled. The I3CxPG register is not allowed to change during operation.
| Name: | I3CxPG |
| Offset: | 0x7A9574 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DDLYEN | DDLYNUMC[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DFLTEN | PGSMPL[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 1 | 1 | 1 | 0 | ||||
Bit 12 – DDLYEN Digital Delay Enable bit
| Value | Description |
|---|---|
| 1 | SDA output delay enable. |
| 0 | SDA output delay disabled. |
Bits 11:8 – DDLYNUMC[3:0] Digital Delay Cycle Number bits
Bit 4 – DFLTEN Digital Filter Enable bit
| Value | Description |
|---|---|
| 1 | Enabled 50 ns spike filter. |
| 0 | Disabled 50 ns spike filter. |