24.3.9 Data Buffer Threshold Control Register

Name: I3CxBUFTHLD
Offset: 0x7A9020

Bit 3130292827262524 
      RXSTARTTHLD[2:0] 
Access R/WR/WR/W 
Reset 001 
Bit 2322212019181716 
      TXSTARTTHLD[2:0] 
Access R/WR/WR/W 
Reset 001 
Bit 15141312111098 
      RXTHLD[2:0] 
Access R/WR/WR/W 
Reset 001 
Bit 76543210 
      TXTHLD[2:0] 
Access R/WR/WR/W 
Reset 001 

Bits 26:24 – RXSTARTTHLD[2:0] Receive Start Threshold Value bits

ValueDescription
100 Controller initiates read transfer/Target ACK's write request whenever RX FIFO has a minimum of 32 empty locations.
011 Controller initiates read transfer/Target ACK's write request whenever RX FIFO has a minimum of 16 empty locations.
010 Controller initiates read transfer/Target ACK's write request whenever RX FIFO has a minimum of 8 empty locations.
001 Controller initiates read transfer/Target ACK's write request whenever RX FIFO has a minimum of 4 empty locations.
000 Controller initiates read transfer/Target ACK's write request whenever RX FIFO has at least one empty location.

Bits 18:16 – TXSTARTTHLD[2:0] Transfer Start Threshold Value bits

ValueDescription
100 Controller initiates write transfer/Target ACK's read request whenever TX FIFO has at least 32 entries.
011 Controller initiates write transfer/Target ACK's read request whenever TX FIFO has at least 16 entries.
010 Controller initiates write transfer/Target ACK's read request whenever TX FIFO has at least 8 entries.
001 Controller initiates write transfer/Target ACK's read request whenever TX FIFO has at least 4 entries.
000 Controller initiates write transfer/Target ACK's read request whenever TX FIFO has at least 1 entry.

Bits 10:8 – RXTHLD[2:0] Receive Buffer Threshold Value bits

ValueDescription
100 Whenever RX FIFO has a minimum of 32 entries, it triggers the RXTHLDSTA interrupt.
011 Whenever RX FIFO has a minimum of 16 entries, it triggers the RXTHLDSTA interrupt.
010 Whenever RX FIFO has a minimum of 8 entries, it triggers the RXTHLDSTA interrupt.
001 Whenever RX FIFO has a minimum of 4 entries, it triggers the RXTHLDSTA interrupt.
000 Whenever RX FIFO has at least one entry, it triggers the RXTHLDSTA interrupt.

Bits 2:0 – TXTHLD[2:0] Transmit Buffer Threshold Value bits

ValueDescription
100 Whenever TX FIFO has a minimum of 32 empty locations, it triggers the TXTHLDSTA interrupt.
011 Whenever TX FIFO has a minimum of 16 empty locations, it triggers the TXTHLDSTA interrupt.
010 Whenever TX FIFO has a minimum of 8 empty locations, it triggers the TXTHLDSTA interrupt.
001 Whenever TX FIFO has a minimum of 4 empty locations, it triggers the TXTHLDSTA interrupt.
000 Whenever TX FIFO has at least one empty location, it triggers the TXTHLDSTA interrupt.