24.3.16 Interrupt Force Enable
Register
| Name: | I3C1INTFORCE |
| Offset: | 0x7A9048 |
Individual
interrupts can be forcefully triggered if the corresponding Force Enable bit is set,
provided the corresponding bit in the I3CxINTSTACON register is
set.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | EXTCMDTXTHLDFRC | EXTCMDFRC | SDARELFRC | GRPADDRFRC | TRSTPATFRC | STARTFRC | |
| Access | | | W | W | W | W | W | W | |
| Reset | | | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | BUSRSTFRC | | BUSOWNFRC | IBIUPDFRC | READREQFRC | DEFTGTFRC | TRANSERRFRC | DYNADDRFRC | |
| Access | W | | W | W | W | W | W | W | |
| Reset | 0 | | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | CCCUPDFRC | TRANSABTFRC | RESPQFRC | CMDQFRC | IBITHLDFRC | RXTHLDFRC | TXTHLDFRC | |
| Access | | W | W | W | W | W | W | W | |
| Reset | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 21 – EXTCMDTXTHLDFRC I3CxEXTCMDy
Transmit Buffer Threshold Force Enable bit
This field is used
in Target mode of operation.
Bit 20 – EXTCMDFRC I3CxEXTCMDy has
Finished Force Enable bit
This field is used in Target
mode of operation.
Bit 19 – SDARELFRC SDA Released from
Stuck State Force Enable bit
This field is used in Target
mode of operation.
Bit 18 – GRPADDRFRC Group Address
Assigned Force Enable bit
This field is used in Target
mode of operation.
Bit 17 – TRSTPATFRC Target Reset
Pattern Detection Interrupt Force Enable bit
This field is used in Target
mode of operation.
Bit 16 – STARTFRC START Detection
Force Enable bit
This field is used in Target
mode of operation.
Bit 15 – BUSRSTFRC Bus Reset Pattern
Generation Done Force Enable bit
This field is used in
Controller mode of operation.
Bit 13 – BUSOWNFRC Bus Owner Updated
Force Enable bit
Bit 12 – IBIUPDFRC IBI Updated Force
Enable bit
This field is used in Target
mode of operation.
Bit 11 – READREQFRC Read Request
Received Force Enable bit
This field is used in Target
mode of operation.
Bit 10 – DEFTGTFRC Define Target CCC
Received Force Enable bit
Bit 9 – TRANSERRFRC Transfer Error
Force Enable bit
Bit 8 – DYNADDRFRC Dynamic Address
Assigned Force Enable bit
This field is used in Target
mode of operation.
Bit 6 – CCCUPDFRC CCC Table Updated
Force Enable bit
This field is used in Target
mode of operation.
Bit 5 – TRANSABTFRC Transfer Abort
Force Enable bit
This field is used in
Controller mode of operation.
Bit 4 – RESPQFRC Response Queue
Ready Force Enable bit
Bit 3 – CMDQFRC Command Queue Ready
Force Enable bit
Bit 2 – IBITHLDFRC IBI Buffer
Threshold Force Enable bit
This field is used in
Controller mode of operation.
Bit 1 – RXTHLDFRC Receive Buffer
Threshold Force Enable bit
Bit 0 – TXTHLDFRC Transmit Buffer
Threshold Force Enable bit
