24.3.2 Device Address Register

Note: This register is used to program device Dynamic Addresses and their respective valid bits in the Controller mode of operation. The software Reset will not clear this register. In the Target mode of operation, this register reflects the Static and Dynamic Addresses and their respective valid bits.
Name: I3CxADD
Offset: 0x7A9004

Bit 3130292827262524 
 DYNADDRVALID        
Access R/W 
Reset 0 
Bit 2322212019181716 
  DYNADDR[6:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 15141312111098 
 STATADDRVALID        
Access R/W 
Reset 0 
Bit 76543210 
  STATADDR[6:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 31 – DYNADDRVALID Dynamic Address Valid bit

ValueDescription
1 Dynamic Address is valid.
0 Dynamic Address is invalid.

Bits 22:16 – DYNADDR[6:0] Device Dynamic Address bits

Bit 15 – STATADDRVALID Static Address Valid bit

ValueDescription
1 Static Address is valid.
0 Static Address is invalid.

Bits 6:0 – STATADDR[6:0] Device Static Address bits