24.3.11 Reset Control Register
| Name: | I3CxRSTCON |
| Offset: | 0x7A9034 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| BUSRST | RSTTYP[2:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IBIQRST | RXFIFORST | TXFIFORST | RESPQRST | CMDQRST | SOFTRST | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 31 – BUSRST Bus Reset bit (Controller mode only)
| Value | Description |
|---|---|
| 1 | Bus Reset pattern generation based on Bus Reset type selection. |
| 0 | Bus Reset pattern generation is completed. |
Bits 30:28 – RSTTYP[2:0] Bus Reset type bit
| Value | Description |
|---|---|
| 110 | SCL LOW RESET pattern |
| 001 | Target Reset pattern |
| 000 | Exit pattern |
Bit 5 – IBIQRST IBI Queue Software Reset bit (Controller mode only)
| Value | Description |
|---|---|
| 1 | Generate IBI Queue Reset. |
| 0 | IBI Queue Reset complete. |
Bit 4 – RXFIFORST Receive Buffer Software Reset bit
| Value | Description |
|---|---|
| 1 | Generate Receive Buffer Reset. |
| 0 | Receive Buffer Reset complete. |
Bit 3 – TXFIFORST Transmit Buffer Software Reset bit
| Value | Description |
|---|---|
| 1 | Generate Transmit Buffer Reset. |
| 0 | Transmit Buffer Reset complete. |
Bit 2 – RESPQRST Response Queue Software Reset bit
| Value | Description |
|---|---|
| 1 | Generate Response Queue Reset. |
| 0 | Response Queue Reset complete. |
Bit 1 – CMDQRST Command Queue Software Reset bit
| Value | Description |
|---|---|
| 1 | Generate Command Queue Reset. |
| 0 | Command Queue Reset complete. |
Bit 0 – SOFTRST Core Software Reset bit
| Value | Description |
|---|---|
| 1 | Generate software (Queues, buffers, programmable registers, pipelining data, state machine to Idle state) Reset. |
| 0 | Command Queue Reset complete. |