This register is applicable only
in Controller mode.
Name:
I3CxCNTRLTIMOUT
Offset:
0x7A90DC
Bit
31
30
29
28
27
26
25
24
TIMOUTCNT[25:24]
Access
R/W
R/W
Reset
0
0
Bit
23
22
21
20
19
18
17
16
TIMOUTCNT[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
1
1
0
1
0
1
Bit
15
14
13
12
11
10
9
8
TIMOUTCNT[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
1
0
0
1
0
1
Bit
7
6
5
4
3
2
1
0
TIMOUTCNT[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
0
1
0
0
0
0
0
Bits 25:0 – TIMOUTCNT[25:0]
This count defines
the number of peripheral clock periods to count for the generation of the SCL Low
Bus Reset Pattern.
DS70005629B
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