24.3.32 Target IBI Response Register
Note:
- The value in this field will indicate the number of bytes remaining that were not transmitted because the Controller terminated the SIR transfer early.
| Name: | I3CxTGTIBIRESP |
| Offset: | 0x7A9098 |
This register reflects the IBI status and the number of data bytes remaining due to early termination.
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SIRRESPDATLEN[14:8] | |||||||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| SIRRESPDATLEN[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IBISTAT[1:0] | |||||||||
| Access | R | R | |||||||
| Reset | 0 | 0 | |||||||
Bits 22:8 – SIRRESPDATLEN[14:0] Data Length for SIR Response bits(1)
Bits 1:0 – IBISTAT[1:0] IBI Completion Status bits
| Value | Description |
|---|---|
| 11 | IBI not attempted. |
| 10 | Controller Early Terminate (only for SIR with data). |
| 01 | IBI accepted by the Controller (ACK response received) . |
| 00 | Reserved |