24.3.46 Target HDR Flow Control Register

Name: I3CxHDRFLWCON
Offset: 0x7A90F0

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 DDRCRCWDIND[1:0]DDRWREARLYTERMNDDRWRACKNACK     
Access RRRR 
Reset 1110 

Bits 7:6 – DDRCRCWDIND[1:0]

Indicates whether the CRC word follows an early termination.
ValueDescription
011 No CRC word follows early termination.
010 Reserved
001 CRC word follows early termination.
000 Reserved

Bit 5 – DDRWREARLYTERMN

Indicates the capability of the Target for WRITE early termination requests.
ValueDescription
1 The Target does not have early-termination capability
0 The Target has early-termination capability

Bit 4 – DDRWRACKNACK

Indicates the capability of the Target to ACK/NACK DDR write commands.
ValueDescription
1 The Target does not have ACK/NACK capability.
0 The Target has ACK/NACK capability.