24.3.26 Target Mode Characteristic Register
Note:
- This field is set to 1 by default, Controller capable. If the application chooses to operate as "Target only" through programming, then the Device Role can be overwritten as Target (BCR[7:6] = 2'b00).
- Programming this field to 0 does not disable the HDR feature itself. This bit can be modified by the application if it does not want to advertise Target HDR capability to the Controller.
| Name: | I3CxTGTCON |
| Offset: | 0x7A9078 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| HDRCAP[7:0] | |||||||||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DCR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DEVICEROLE[1:0] | SDRHDR | BRGID | OFFLINECAP | IBIPYLD | IBIREQCAP | MAXDATSPDLMT | |||
| Access | R/W | R/W | R/W | R | R | R | R | R/W | |
| Reset | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | |
Bits 23:16 – HDRCAP[7:0] I3C Device HDR Capability Register Value bits
| Value | Description |
|---|---|
| 11111111 - 00000010 | Reserved |
| 00000001 | HDR- DDR capable |
| 00000000 | Reserved |
Bits 15:8 – DCR[7:0] I3C Device Characteristic Value bits
Bits 7:6 – DEVICEROLE[1:0] Device Role Field in Bus Characteristic Register (BCR[7:6])(1) bits
Bit 5 – SDRHDR SDR Only or SDR and HDR Capable Field in Bus (BCR[5])(2) bit
| Value | Description |
|---|---|
| 1 | HDR DDR capable. |
| 0 | SDR capable. |
Bit 4 – BRGID Bridge Identifier Field in Bus Characteristic Register (BCR[4]) bit
| Value | Description |
|---|---|
| 1 | Virtual Target, or exposes other downstream device(s). |
| 0 | Not a Virtual Target and does not expose any other downstream device(s). |
Bit 3 – OFFLINECAP Offline Capable Field in Bus Characteristic Register (BCR[3]) bit
| Value | Description |
|---|---|
| 1 | Target will not always respond to I3C Bus commands. |
| 0 | Target will always respond to I3C Bus commands. |
Bit 2 – IBIPYLD IBI Payload Field in Bus Characteristic Register bit (BCR[2])
| Value | Description |
|---|---|
| 1 | One data byte (MDB) shall follow the accepted IBI, and additional data bytes may follow. |
| 0 | No data bytes follow the accepted IBI. |
Bit 1 – IBIREQCAP IBI Request Capable Field in Bus Characteristic Register bit (BCR[1])
| Value | Description |
|---|---|
| 1 | Capable |
| 0 | Not capable. |
Bit 0 – MAXDATSPDLMT Max Data Speed Limitation Field in Bus Characteristic Register bit (BCR[0])
| Value | Description |
|---|---|
| 1 | Target returns the data in the I3CxCLTDATSPD and I3CxCLTIBIPYLD registers in response to the GETMXDS CCC sent by the Controller. |
| 0 | Target NACKs the GETMXDS CCC sent by the Controller. |