24.3.15 Interrupt Signal Enable
Register
| Name: | I3CxINTCON |
| Offset: | 0x7A9044 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | EXTCMDTXTHLDINTEN | EXTCMDINTEN | SDARELINTEN | GRPADDRINTEN | TRSTPATINTEN | STARTINTEN | |
| Access | | | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | | | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | BUSRSTINTEN | | BUSOWNINTEN | IBIUPDINTEN | READREQINTEN | DEFTGTINTEN | TRANSERRINTEN | DYNADDRINTEN | |
| Access | R/W | | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | CCCUPDINTEN | TRANSABTINTEN | RESPQINTEN | CMDQINTEN | IBITHLDINTEN | RXTHLDINTEN | TXTHLDINTEN | |
| Access | | R/W | R/W | R/W | R/W | R | R/W | R/W | |
| Reset | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 21 – EXTCMDTXTHLDINTEN I3CxEXTCMDy
Transmit Buffer Threshold Signal Enable bit
This field is used
in Target mode of operation.
Bit 20 – EXTCMDINTEN I3CxEXTCMDy has
Finished Signal Enable bit
This field is used in Target
mode of operation.
Bit 19 – SDARELINTEN SDA Released from
Stuck State Signal Enable bit
This field is used in Target
mode of operation.
Bit 18 – GRPADDRINTEN Group Address
Assigned Signal Enable bit
This field is used in Target
mode of operation.
Bit 17 – TRSTPATINTEN Target Reset
Pattern Detection Signal Enable bit
This field is used in Target
mode of operation.
Bit 16 – STARTINTEN START Detection
Signal Enable bit
This field is used in Target
mode of operation.
Bit 15 – BUSRSTINTEN Bus Reset Pattern
Generation Done Signal Enable bit
This field is used in
Controller mode of operation.
Bit 13 – BUSOWNINTEN Bus Owner Updated
Signal Enable bit
Bit 12 – IBIUPDINTEN IBI Updated Signal
Enable bit
This field is used in Target
mode of operation.
Bit 11 – READREQINTEN Read Request
Received Signal Enable bit
This field is used in Target
mode of operation.
Bit 10 – DEFTGTINTEN Define Target CCC
Received Signal Enable bit
Bit 9 – TRANSERRINTEN Transfer Error
Signal Enable bit
Bit 8 – DYNADDRINTEN Dynamic Address
Assigned Signal Enable bit
This field is used in Target
mode of operation.
Bit 6 – CCCUPDINTEN CCC Table Updated
Signal Enable bit
This field is used in Target
mode of operation.
Bit 5 – TRANSABTINTEN Transfer Abort
Signal Enable bit
This field is used in
Controller mode of operation.
Bit 4 – RESPQINTEN Response Queue
Ready Signal Enable bit
Bit 3 – CMDQINTEN Command Queue Ready
Signal Enable bit
Bit 2 – IBITHLDINTEN IBI Buffer
Threshold Signal Enable bit
This field is used in
Controller mode of operation.
Bit 1 – RXTHLDINTEN Receive Buffer
Threshold Signal Enable bit
Bit 0 – TXTHLDINTEN Transmit Buffer
Threshold Signal Enable bit
